Skyworks Solutions Inc. SI86S631EC-AS1R
- Part No.:
- SI86S631EC-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86S631EC-AS1R.pdf
- Description:
- 3.75 KVRMS ISOLATOR, 3 UNIDIRECT
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86S631EC-AS1R from Skyworks Solutions is a 3-channel, reinforced digital isolator with 6000 VRMS isolation rating, 150 Mbps data rate, and AEC-Q100 qualification for automotive systems. It features Schmitt-trigger + CMOS inputs, tri-state outputs with enable, selectable fail-safe default-high/low output, and operates across –40 to 125 °C in WB SOIC-16 package. Used in battery management systems and traction inverters where high noise immunity and safety-certified signal isolation are critical.
For engineers reviewing the SI86S631EC-AS1R datasheet, SI86S631EC-AS1R pinout, SI86S631EC-AS1R application, or SI86S631EC-AS1R equivalent, key selection criteria include reinforced IEC 60747-17 certification, 10 ns typical propagation delay, 3.5 ns pulse width distortion, transient immunity ≥100 kV/µs, and dual supply operation (2.25–5.5 V per side) supporting isolated SPI interfaces and motor control feedback loops.
Technical Context
The SI86S631EC-AS1R implements RF-based on/off keying modulation across a semiconductor isolation barrier, eliminating start-up initialization and enabling robust noise immunity without optical degradation. Its architecture supports independent UVLO and reset monitoring on both sides (VDD1/VDD2), with RSTB thresholds at ~1.7 V and UVLO+ at 2.18 V.
It provides three unidirectional isolated channels (A1→B1, A2→B2, A3→B3), side-specific enable pins (EN1, EN2), and failsafe configuration via ordering option - default high or low output during input-side power loss while output side remains powered.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | DC to 150 Mbps - supports high-speed serial links including isolated SPI clock domains up to 75 MHz. |
| Isolation rating | 6000 VRMS (1 min) - meets reinforced insulation requirements per UL 1577 and IEC 60747-17 for automotive and industrial safety-critical applications. |
| Propagation delay | 10 ns typical - enables precise timing alignment in closed-loop motor control and real-time ADC/DAC isolation paths. |
| Pulse width distortion | 3.5 ns typical - preserves duty cycle integrity for PWM signals and clock forwarding across isolation boundary. |
| Supply voltage | 2.25–5.5 V per side - allows interoperability with 3.3 V and 5 V logic families on both isolated sides without level shifters. |
| Transient immunity | ≥100 kV/µs - ensures reliable operation in high dv/dt environments such as SiC/GaN inverter gate drive circuits. |
| Operating temperature | –40 to 125 °C - qualified for under-hood automotive use including onboard chargers and battery electric vehicle power stages. |
Pinout & Package
SI86S631EC-AS1R is housed in a wide-body SOIC-16 (WB SOIC-16) package with creepage/clearance optimized for 6000 VRMS reinforced insulation. Pin 1 is marked with a dot; pin numbering follows standard SOIC convention (counterclockwise from top-left corner).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (EN1) | Side A output enable | Active-high control for tristating all Side A outputs (A1–A3); used for synchronized shutdown of isolated interface. |
| 2 (VDD1) | Side A supply | 2.25–5.5 V power for input-side circuitry; requires 0.1 µF + 10 µF bypass capacitors placed near pin. |
| 3 (A1) | Side A input channel 1 | Unidirectional isolated input (A→B); accepts Schmitt-trigger + CMOS thresholds for noise-immune signal coupling. |
| 4 (A2) | Side A input channel 2 | Unidirectional isolated input (A→B); compatible with 3.3 V/5 V logic; no external bias required. |
| 5 (A3) | Side A input channel 3 | Unidirectional isolated input (A→B); supports fail-safe default state selection during VDD1 undervoltage. |
| 6 (NC) | No connect | Internally unused; must be left floating or grounded per layout guidelines to avoid parasitic coupling. |
| 7–8 (GND1) | Side A ground | Reference return path for VDD1; must be routed separately from GND2 to maintain isolation integrity. |
| 9 (B1) | Side B output channel 1 | Corresponding isolated output for A1; 50 Ω nominal output impedance suitable for controlled-impedance PCB traces. |
| 10 (B2) | Side B output channel 2 | Corresponding isolated output for A2; supports tri-state when EN2 = low; maintains fail-safe state during VDD1 loss. |
| 11 (B3) | Side B output channel 3 | Corresponding isolated output for A3; default state (high/low) determined by ordering option EC (default high). |
| 12 (EN2) | Side B output enable | Active-high control for tristating all Side B outputs (B1–B3); enables bidirectional bus arbitration in custom designs. |
| 13–14 (GND2) | Side B ground | Reference return path for VDD2; physically separated from GND1 by isolation barrier; requires dedicated plane. |
| 15 (VDD2) | Side B supply | 2.25–5.5 V power for output-side circuitry; independent of VDD1; enables asymmetric supply configurations. |
| 16 (HF) | High-frequency test pad | Factory test access point; not connected in normal operation; must be left unconnected on PCB. |
Key Features
| Feature | Design Value |
|---|---|
| Reinforced IEC 60747-17 rating | Validated for 6000 VRMS working voltage - satisfies reinforced insulation requirements in medical (60601-1) and industrial (62368-1) end-equipment standards. |
| Tri-state outputs with enable | EN1/EN2 pins allow dynamic disabling of all outputs on respective sides - essential for shared-bus isolation and hot-swap compatibility. |
| Selectable fail-safe mode | EC suffix denotes default-high output during VDD1 loss - prevents undefined states in safety-critical feedback paths like inverter fault signaling. |
| Schmitt-trigger + CMOS inputs | Hysteresis ≥0.15 × VDDx - rejects fast transients and EFT noise without external filtering, reducing BOM count in noisy motor drive environments. |
| AEC-Q100 Grade 1 qualification | Qualified for automotive ambient temperatures up to 125 °C - supports deployment in traction inverters and onboard chargers without derating. |
Applications
| Battery Management System (BMS) | Traction Inverter Control |
|---|---|
|
Use Scenario: Isolating cell voltage monitoring and pack current sensing signals between high-voltage battery stack and MCU-based controller. IC Role / Device Role / Timing Role: SI86S631EC-AS1R provides three independent isolated channels for analog front-end (AFE) communication, enabling simultaneous sampling of voltage, temperature, and current telemetry across isolation barrier. Use Value: 6000 VRMS reinforced isolation ensures compliance with ISO 26262 ASIL-C requirements; 10 ns propagation delay preserves timing correlation between sampled parameters for accurate state-of-charge estimation. |
Use Scenario: Transmitting PWM gate drive commands and fault feedback from MCU to isolated gate drivers in SiC-based traction inverters. IC Role / Device Role / Timing Role: SI86S631EC-AS1R carries three unidirectional control signals - high-side enable, low-side enable, and fault clear - across isolation barrier with deterministic latency. Use Value: 150 Mbps data rate supports multi-level PWM schemes; ≥100 kV/µs CMTI withstand ensures immunity against fast-switching dv/dt noise in 800 V battery systems. |
| Onboard Charger (OBC) Communication | Isolated SPI Interface for ADC/DAC |
|
Use Scenario: Isolating CAN or UART communication lines between OBC primary-side controller and secondary-side DC-DC converter supervisor IC. IC Role / Device Role / Timing Role: SI86S631EC-AS1R routes UART TX/RX and enable signals across isolation barrier, maintaining galvanic separation between AC-input and DC-output domains. Use Value: Dual 2.25–5.5 V supply range allows direct interfacing with 3.3 V microcontrollers and 5 V level-shifted transceivers; AEC-Q100 qualification ensures reliability over 15-year OBC lifetime. |
Use Scenario: Isolating serial interface between microcontroller and isolated precision ADC (e.g., AD7403) or DAC in industrial motor drives. IC Role / Device Role / Timing Role: SI86S631EC-AS1R carries SCLK, MOSI, and MISO signals across isolation barrier, preserving SPI timing integrity for 16-bit conversion cycles. Use Value: 3.5 ns pulse width distortion minimizes clock duty cycle error; fail-safe default-high output prevents spurious writes during MCU reset sequences. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM1311BRWZ | 3-channel, 100 Mbps, 3750 VRMS, SOIC-16, non-AEC-Q100 | Limited to industrial temp range (–40 to 105 °C); lacks reinforced IEC 60747-17 rating and automotive qualification | Acceptable for cost-sensitive industrial PLCs but unsuitable for automotive BMS or traction inverter deployments requiring ASIL compliance. |
| ISO6731FDWR | 3-channel, 50 Mbps, 5000 VRMS, SOIC-16, AEC-Q100 Grade 1 | Lower data rate and isolation rating; uses capacitive isolation; no selectable fail-safe mode | Valid for lower-speed automotive sub-systems (e.g., HVAC control), but cannot support high-bandwidth feedback loops in 800 V inverters. |
Compared with ADUM1311BRWZ and ISO6731FDWR, the SI86S631EC-AS1R delivers higher isolation (6000 VRMS), faster data rate (150 Mbps), and guaranteed fail-safe behavior - making it uniquely suited for safety-critical automotive power electronics where timing determinism and regulatory compliance are non-negotiable.
Availability
SI86S631EC-AS1R is available at Aetrix Electronics and suitable for battery management systems, traction inverters, and onboard chargers requiring stable component supply across automotive production lifecycles.
Supply support for SI86S631EC-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in high-performance analog semiconductors, specializing in RF, timing, and isolation technologies for wireless, automotive, and industrial markets.
The Si86S6xx family was engineered specifically for automotive-grade digital isolation - delivering reinforced safety certification, extended temperature operation, and RF-based noise immunity to replace optocouplers in next-generation EV power systems.
FAQ
What is the isolation rating and safety certification status of SI86S631EC-AS1R?
The SI86S631EC-AS1R is rated for 6000 VRMS isolation per UL 1577 (1 minute) and certified to IEC 60747-17 for reinforced insulation. It holds pending CSA 62368-1 and VDE 60747-17 approvals, and is fully AEC-Q100 Grade 1 qualified for automotive use. These certifications are validated for the WB SOIC-16 package variant shipped as SI86S631EC-AS1R.
Does SI86S631EC-AS1R support fail-safe operation, and how is it configured?
Yes, SI86S631EC-AS1R supports selectable fail-safe mode via ordering code: the "EC" suffix indicates default-high output state when VDD1 is unpowered but VDD2 remains active. This behavior is hardwired per device variant and does not require external configuration. The SI86S631EC-AS1R maintains this state until VDD1 rises above UVLO+ (2.18 V).
What are the supply voltage requirements for SI86S631EC-AS1R on each side of the isolation barrier?
SI86S631EC-AS1R operates with independent supplies: VDD1 and VDD2 each accept 2.25 V to 5.5 V over temperature. Both supplies must be bypassed with 0.1 µF ceramic + 10 µF bulk capacitors placed adjacent to their respective pins. The device functions correctly with asymmetric supplies - e.g., 3.3 V on Side A and 5 V on Side B.
How does SI86S631EC-AS1R handle power-up sequencing when VDD1 and VDD2 power up at different times?
SI86S631EC-AS1R incorporates independent UVLO and reset monitors on each side. If VDD1 powers up before VDD2, outputs remain in fail-safe state (high for EC variant) until VDD2 exceeds UVLO+. If VDD2 powers up first, outputs enter high-impedance state until VDD1 stabilizes. Startup time from unpowered to valid output is 0.3 ms after both supplies exceed UVLO+.
Can SI86S631EC-AS1R be used in SPI isolation applications, and what are its limitations?
SI86S631EC-AS1R supports basic isolated SPI signal routing (e.g., SCLK, MOSI, MISO) across its three channels, but lacks dedicated SPI control logic like chip select or direction handling found in Si86SSx or Si86SQx variants. For full SPI isolation, Skyworks recommends Si86SS41 or Si86SS51; SI86S631EC-AS1R is best suited for discrete signal isolation within SPI subsystems.
SI86S631EC-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 3
- Inputs - Side 1/Side 2:
- 2/1
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 42ns, 42ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86S631EC-AS1R FAQ
1.How can I place an order for SI86S631EC-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86S631EC-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86S631EC-AS1R reliable?
The price and inventory of SI86S631EC-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86S631EC-AS1R is usually 5 days.
3.What payment methods are accepted for SI86S631EC-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86S631EC-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86S631EC-AS1R?
SI86S631EC-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86S631EC-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86S631EC-AS1R?
For technical support, including SI86S631EC-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86S631EC-AS1R requirements.
6.How does Aetrix verify that SI86S631EC-AS1R is sourced from the original manufacturer or authorized distributors?
All SI86S631EC-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86S631EC-AS1R meets industry standards.
7.What is the process for return or replacement of SI86S631EC-AS1R?
All SI86S631EC-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI86S631EC-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86S631EC-AS1R part is unused and in its original packaging.
Return procedure for SI86S631EC-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86S631EC-AS1R Tags
-
ISO1212DBQR
Texas Instruments

-
ISO6721BDR
Texas Instruments

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SI8710AC-B-ISR
Skyworks Solutions Inc.

-
ISO7720FDR
Texas Instruments

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ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

-
SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

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ISO7721DWVR
Texas Instruments
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ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
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