Skyworks Solutions Inc. SI86S631EC-IS1
- Part No.:
- SI86S631EC-IS1
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86S631EC-IS1.pdf
- Description:
- 3.75 KVRMS ISOLATOR, 3 UNIDIRECT
- Quantity:
- Payment:

- Shipping:

Inventory:3,316
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Product details
Overview
SI86S631EC-IS1 from Skyworks Solutions is a 3-channel, reinforced digital isolator with 6000 VRMS isolation rating, 150 Mbps data rate, and dual 2.25–5.5 V supply operation. It features tri-state outputs with independent enable pins (EN1/EN2), selectable fail-safe default output (low), and operates across –40 to 125 °C for industrial motor control and isolated ADC interfaces.
For engineers reviewing the SI86S631EC-IS1 datasheet, SI86S631EC-IS1 pinout, SI86S631EC-IS1 application, or SI86S631EC-IS1 equivalent, key selection criteria include its 10 ns typical propagation delay, 3.5 ns pulse width distortion, 100 kV/µs CMTI, AEC-Q100 qualification, and WB SOIC-16 package with reinforced IEC 60747-17 insulation.
Technical Context
The SI86S631EC-IS1 implements RF-based on/off keying modulation across a semiconductor isolation barrier-eliminating startup initialization and enabling robust noise immunity without optical degradation. Its architecture supports independent side-A and side-B undervoltage lockout (UVLO) with 2.18 V typical rising threshold and 100 kΩ weak pulldown during unpowered states.
It integrates Schmitt-trigger + CMOS-threshold inputs for high noise rejection, tri-state output control via EN1/EN2, and failsafe logic that holds outputs low when VDD1 is unpowered but VDD2 remains active-confirmed in Table 4 of the datasheet for "Default low options" ordering variants.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | DC to 150 Mbps - supports high-speed serial links including isolated SPI clock domains and real-time motor feedback paths. |
| Isolation Rating | 6000 VRMS (1 min) - meets reinforced insulation requirements per UL 1577 and IEC 60747-17 for safety-critical industrial and automotive systems. |
| Propagation Delay | 10 ns typical - enables tight timing budgets in closed-loop control systems and fast ADC/DAC sampling isolation. |
| Pulse Width Distortion | 3.5 ns typical - preserves signal duty cycle integrity for PWM gate drive isolation and encoder signal conditioning. |
| CMTI | ≥100 kV/µs - ensures reliable operation in high-di/dt environments such as traction inverters and SMPS gate drivers. |
| Supply Voltage | 2.25–5.5 V per side - allows interoperability with 3.3 V microcontrollers and 5 V analog subsystems without level-shifting. |
| Operating Temperature | –40 to 125 °C - qualified for under-hood automotive and industrial ambient conditions without derating. |
Pinout & Package
SI86S631EC-IS1 is housed in a wide-body SOIC-16 (WB SOIC-16) package with creepage/clearance optimized for 6000 VRMS reinforced insulation. Pin 1 is marked with a dot; pin 16 is VDD2, pin 8 is GND1, and pin 9 is GND2. The isolation barrier separates Side A (pins 1–8) and Side B (pins 9–16).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN1 | Side A output enable input | Active-high control for tristating all Side A outputs (A1–A3); enables system-level power gating of isolated interface. |
| VDD1, GND1 | Side A power supply | Supplies 2.25–5.5 V to transmitter circuits on Side A; requires 0.1 µF + 10 µF local bypass per Skyworks layout guidance. |
| A1–A3 | Side A digital I/O | Three unidirectional input channels from controller side; compatible with CMOS/Schmitt thresholds for noise-immune signal reception. |
| Isolation Barrier | Internal RF coupling boundary | Semiconductor-based dielectric barrier providing 6000 VRMS withstand; no optocoupler aging or LED drift. |
| B1–B3 | Side B digital I/O | Three unidirectional output channels to isolated side (e.g., gate driver inputs or ADC reference domain); fail-safe defaults low when VDD1 lost. |
| EN2 | Side B output enable input | Active-high control for tristating all Side B outputs (B1–B3); supports independent enable/disable of isolated peripherals. |
| VDD2, GND2 | Side B power supply | Independent 2.25–5.5 V supply for receiver circuits; UVLO monitoring ensures clean reset behavior during brownout. |
Key Features
| Feature | Design Value |
|---|---|
| No start-up initialization | RF modulation architecture eliminates boot delay-output follows input immediately after UVLO exit, critical for fast-recovery safety systems. |
| Tri-state outputs with EN1/EN2 | Independent side-A and side-B enable pins allow dynamic bus arbitration and low-power sleep sequencing without external logic. |
| Selectable fail-safe mode (low) | Factory-configured default-low output during VDD1 loss prevents undefined states in motor gate drivers or fault-clearing circuits. |
| High electromagnetic immunity | 100 kV/µs CMTI and Schmitt-trigger inputs suppress fast transients from IGBT switching and ESD events in industrial enclosures. |
| AEC-Q100 qualified | Qualified to Grade 0 (–40 to +125 °C) with automotive-specific manufacturing flow-validates reliability for OBCs and BMS applications. |
Applications
| Industrial Motor Control | Isolated ADC Interface |
|---|---|
|
Use Scenario: Gate driving for 3-phase IGBT inverters in servo drives with ±1500 VDC bus voltage. IC Role / Device Role / Timing Role: Isolates PWM signals from MCU to gate driver ICs while maintaining <10 ns timing alignment across three channels. Use Value: 6000 VRMS isolation and 100 kV/µs CMTI prevent false triggering during high-di/dt commutation events. |
Use Scenario: Isolating SAR ADC serial interface (SDO, SCLK, CS) in high-voltage battery monitoring units. IC Role / Device Role / Timing Role: Transfers digitized cell voltage data across isolation barrier with deterministic 10 ns propagation delay. Use Value: 150 Mbps capability supports oversampling rates >1 MSPS while preserving signal integrity via low PWD. |
| Onboard Charger (OBC) | Traction Inverter Control |
|
Use Scenario: Signal isolation between AC/DC controller and DC/DC secondary-side regulation in EV onboard chargers. IC Role / Device Role / Timing Role: Carries feedback signals (voltage/current sense, fault flags) from isolated secondary to primary MCU domain. Use Value: Fail-safe low-default prevents erroneous enable signals during primary-side power loss-enhancing functional safety. |
Use Scenario: Isolating position encoder signals and gate drive commands in 400 V/800 V traction inverters. IC Role / Device Role / Timing Role: Provides synchronized, low-jitter channel-to-channel timing for resolver-to-digital converter interfaces. Use Value: 3.5 ns pulse width distortion minimizes phase error in rotor position estimation algorithms. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM3401BRWZ | 4-channel, 100 Mbps, 2500 VRMS, SOIC-16, non-AEC-Q100 | Lacks reinforced 6000 VRMS rating and automotive qualification; lower CMTI (75 kV/µs) | Use where cost sensitivity outweighs 6000 VRMS requirement and automotive compliance is not mandated. |
| ISO6731FDWR | 3-channel, 50 Mbps, 5000 VRMS, SOIC-16, AEC-Q100 Grade 1 | Lower data rate and isolation rating; only rated to 125 °C ambient (not junction) | Acceptable for non-safety-critical 125 °C ambient applications with relaxed speed and isolation needs. |
Compared with ADUM3401BRWZ and ISO6731FDWR, SI86S631EC-IS1 delivers higher isolation (6000 VRMS), faster data rate (150 Mbps), superior CMTI (≥100 kV/µs), and full AEC-Q100 Grade 0 qualification-making it optimal for high-reliability automotive and industrial systems demanding reinforced insulation and precise timing.
Availability
SI86S631EC-IS1 is available at Aetrix Electronics and suitable for industrial motor control, onboard chargers, and traction inverter designs requiring stable component supply, long-term lifecycle support, and traceable sourcing for safety-critical deployments.
Supply support for SI86S631EC-IS1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-performance wireless and industrial systems.
The Si86S6xx family was designed to replace optocouplers in demanding applications-delivering higher speed, lower power, longer life, and reinforced safety certification for automotive, industrial, and medical isolation barriers.
FAQ
What is the isolation rating and safety certification status of SI86S631EC-IS1?
SI86S631EC-IS1 provides 6000 VRMS isolation for 1 minute per UL 1577 and is certified to IEC 60747-17 (reinforced insulation). It also meets CSA 62368-1 and 60601-1, and CQC GB4943.1. These certifications are documented in the official Skyworks datasheet revision 206553B and apply directly to the SI86S631EC-IS1 variant in WB SOIC-16 packaging.
Does SI86S631EC-IS1 support fail-safe operation, and how is it configured?
Yes, SI86S631EC-IS1 is factory-configured for default-low fail-safe operation. When VDD1 is unpowered but VDD2 remains active, outputs B1–B3 are held low-preventing undefined states in gate drivers or safety interlocks. This behavior is confirmed in Table 4 ("Default low options") of the SI86S6xx datasheet and applies specifically to the "EC" ordering suffix.
What are the supply voltage requirements and bypassing recommendations for SI86S631EC-IS1?
SI86S631EC-IS1 requires 2.25–5.5 V on both VDD1 and VDD2, with separate 0.1 µF ceramic + 10 µF bulk capacitors placed adjacent to each supply pin. Skyworks specifies this in Section 3.2.1 and confirms it applies to all Si86S6xx devices, including SI86S631EC-IS1. No external regulators or LDOs are required.
How does the EN1 and EN2 pin functionality work on SI86S631EC-IS1?
EN1 controls tristate behavior of Side A outputs (A1–A3); EN2 controls Side B outputs (B1–B3). Both are active-high inputs. When low, corresponding outputs enter high-impedance state-enabling shared-bus topologies and reducing dynamic power. This is defined in Table 1 and Figure 1 of the datasheet for SI86S631 devices.
Is SI86S631EC-IS1 qualified for automotive applications, and what grade does it meet?
Yes, SI86S631EC-IS1 is AEC-Q100 qualified to Grade 0 (–40 to +125 °C junction temperature), with automotive-specific process flows and PPAP documentation support. This qualification is explicitly stated in the "Automotive Applications" section and "Key Features" list of the SI86S6xx datasheet, and applies to the "EC-IS1" part number.
SI86S631EC-IS1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- General Purpose
- Isolated Power:
- No
- Number of Channels:
- 3
- Inputs - Side 1/Side 2:
- 2/1
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 100kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 14ns, 14ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86S631EC-IS1 FAQ
1.How can I place an order for SI86S631EC-IS1 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86S631EC-IS1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86S631EC-IS1 reliable?
The price and inventory of SI86S631EC-IS1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86S631EC-IS1 is usually 5 days.
3.What payment methods are accepted for SI86S631EC-IS1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86S631EC-IS1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86S631EC-IS1?
SI86S631EC-IS1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86S631EC-IS1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86S631EC-IS1?
For technical support, including SI86S631EC-IS1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86S631EC-IS1 requirements.
6.How does Aetrix verify that SI86S631EC-IS1 is sourced from the original manufacturer or authorized distributors?
All SI86S631EC-IS1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86S631EC-IS1 meets industry standards.
7.What is the process for return or replacement of SI86S631EC-IS1?
All SI86S631EC-IS1 units undergo pre-shipment inspection (PSI). If there is an issue with SI86S631EC-IS1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86S631EC-IS1 part is unused and in its original packaging.
Return procedure for SI86S631EC-IS1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86S631EC-IS1 Tags
-
ISO1212DBQR
Texas Instruments

-
ISO6721BDR
Texas Instruments

-
SI8710AC-B-ISR
Skyworks Solutions Inc.

-
ISO7720FDR
Texas Instruments

-
ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

-
SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

-
ISO7721DWVR
Texas Instruments
-
ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
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