Skyworks Solutions Inc. SI86S640BC-AS1R
- Part No.:
- SI86S640BC-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86S640BC-AS1R.pdf
- Description:
- 3.75 KVRMS ISOLATOR, 4 UNIDIRECT
- Quantity:
- Payment:

- Shipping:

Inventory:2,144
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Product details
Overview
SI86S640BC-AS1R from Skyworks Solutions is a 4-channel, reinforced digital isolator with bidirectional signal isolation across a semiconductor barrier, supporting up to 150 Mbps data rate, 10 ns typical propagation delay, and 6000 VRMS isolation rating. It operates from 2.25–5.5 V on both sides and is qualified per AEC-Q100 for automotive onboard chargers and battery management systems.
For engineers reviewing the SI86S640BC-AS1R datasheet, SI86S640BC-AS1R pinout, SI86S640BC-AS1R application, or SI86S640BC-AS1R equivalent, this device delivers precise timing, fail-safe output configuration (default-low), Schmitt-trigger inputs with CMOS thresholds, and high CMTI (>100 kV/µs), making it suitable for isolated ADC interfaces, motor control gate drivers, and high-noise industrial inverters.
Technical Context
The SI86S640BC-AS1R implements RF-based on/off keying modulation across a monolithic semiconductor isolation barrier-eliminating startup initialization and enabling robust noise immunity without optical degradation. Its architecture supports independent undervoltage lockout (UVLO) and reset circuits on both sides (VDD1/VDD2), with RSTB thresholds at ~1.7 V and UVLO hysteresis of 105–160 mV.
All four channels are bidirectional I/O with tri-state enable (EN1/EN2), selectable fail-safe default-low output during unpowered conditions, and integrated 50 Ω nominal output impedance for controlled-impedance PCB routing. Input deglitch filtering (36 ns) is included per the "S64x" family specification, rejecting sub-threshold transients before isolation transmission.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | DC to 150 Mbps - supports high-speed SPI, isolated serial links, and real-time control loops without protocol translation. |
| Propagation delay | 10 ns typical - enables tight timing budgets in closed-loop motor control and fast ADC sampling synchronization. |
| Isolation rating | 6000 VRMS (1 min) - meets reinforced insulation requirements per UL 1577, VDE 60747-17, and IEC 62368-1 for safety-critical systems. |
| Supply voltage | 2.25–5.5 V per side - allows interoperability with 3.3 V microcontrollers and 5 V analog subsystems without level shifters. |
| CMTI | ≥100 kV/µs - ensures reliable operation in high-dV/dt environments like IGBT gate drive circuits and power inverter switching nodes. |
| Operating temperature | –40 to +125 °C - validated for under-hood automotive and industrial ambient conditions without derating. |
| Fail-safe mode | Default-low output - guarantees known state on Side B when Side A supply fails, critical for safe shutdown in BMS and traction inverters. |
Pinout & Package
SI86S640BC-AS1R uses a WB SOIC-16 (wide-body small-outline integrated circuit) package with creepage/clearance optimized for 6000 VRMS working voltage. Pin 1 is marked with a dot; pin numbering follows standard SOIC convention (counterclockwise from top-left corner).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1, GND1 | Side A power supply | Provides isolated 2.25–5.5 V bias for input-side logic; requires 0.1 µF + 10 µF local bypassing. |
| A1–A4 | Side A digital I/O | Bidirectional isolated data channels; accept Schmitt-trigger + CMOS thresholds for noise immunity. |
| EN1 | Side A output enable | Active-high control: drives all A-side outputs into high-impedance when low, enabling bus sharing. |
| VDD2, GND2 | Side B power supply | Independent 2.25–5.5 V bias for output-side logic; decoupling identical to Side A. |
| B1–B4 | Side B digital I/O | Mirror A1–A4 functionality with fail-safe default-low behavior during VDD1 loss. |
| EN2 | Side B output enable | Active-high control: places all B-side outputs in high-Z, allowing multi-device arbitration on shared buses. |
Key Features
| Feature | Design Value |
|---|---|
| No start-up initialization | RF-modulated channel architecture eliminates boot sequence delays-output valid within 0.3 ms of VDD stabilization. |
| Input deglitch filter | 36 ns pulse rejection window removes EFT-induced glitches while preserving signal integrity for real-time control. |
| Tri-state outputs with enable | Dual EN1/EN2 pins allow independent high-Z control per side-essential for daisy-chained SPI or shared isolated buses. |
| Reinforced safety certification | UL 1577, VDE 60747-17, CSA 62368-1, and CQC GB4943.1 approvals reduce system-level safety certification effort. |
| AEC-Q100 Grade 1 | Qualified for automotive applications including onboard chargers and battery management systems with full PPAP support. |
Applications
| Isolated ADC Interface | Motor Control Gate Driver |
|---|---|
|
Use Scenario: Isolating serial interface between MCU and precision SAR ADC in high-voltage battery monitoring. IC Role / Device Role / Timing Role: Bidirectional digital isolator transmitting conversion clock, data, and busy signals across 1 kV potential difference. Use Value: 10 ns propagation delay preserves sampling timing accuracy; 6000 VRMS rating enables direct connection to 800 V battery stacks. |
Use Scenario: Isolating PWM signals from controller to IGBT/SiC gate driver in 3-phase inverter stage. IC Role / Device Role / Timing Role: High-CMTI channel delivering dead-time-critical gate pulses with minimal skew between phases. Use Value: ≥100 kV/µs common-mode transient immunity prevents false triggering during 10 kV/µs switching transients. |
| Onboard Charger (OBC) | Battery Management System (BMS) |
|
Use Scenario: Signal isolation between AC/DC controller and DC/DC secondary side in EV onboard charger. IC Role / Device Role / Timing Role: Reinforced isolator carrying feedback, fault reporting, and synchronous rectifier control across primary-secondary barrier. Use Value: AEC-Q100 qualification and –40 to +125 °C operation ensure reliability in under-hood thermal cycling. |
Use Scenario: Isolating cell voltage measurement ICs from main BMS controller in 96-cell lithium pack. IC Role / Device Role / Timing Role: Four-channel isolator transmitting multiplexed ADC data, balancing commands, and thermal alerts. Use Value: Default-low fail-safe mode forces safe discharge path activation if MCU supply fails during overvoltage event. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM4402BRIZ | 4-channel, 100 Mbps, 2.5 kVRMS, 15 ns propagation delay, no deglitch filter | Limited to industrial (not AEC-Q100) and lower isolation voltage; lacks 36 ns input filtering | Choose ADUM4402BRIZ only if 2.5 kVRMS suffices and automotive qualification is unnecessary. |
| ISO6741FDWR | 4-channel, 50 Mbps, 5 kVRMS, 25 ns propagation delay, no fail-safe default-low option | Lower speed and timing performance; no configurable fail-safe state-outputs float or latch unpredictably during brownout | Select ISO6741FDWR only for cost-sensitive non-safety-critical designs where 50 Mbps and no fail-safe are acceptable. |
Compared with ADUM4402BRIZ and ISO6741FDWR, SI86S640BC-AS1R provides higher isolation (6000 VRMS), faster timing (10 ns vs. 15/25 ns), automotive qualification, and deterministic fail-safe behavior-making it the preferred choice for OBC, BMS, and high-reliability industrial inverters.
Availability
SI86S640BC-AS1R is available at Aetrix Electronics and suitable for automotive onboard chargers, battery management systems, and isolated motor control inverters requiring stable component supply across extended product lifecycles.
Supply support for SI86S640BC-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-performance wireless and power systems.
The Si86S6xx family was designed specifically for high-reliability, high-speed digital isolation in automotive and industrial applications-emphasizing reinforced safety, low-latency timing, and robust electromagnetic immunity.
FAQ
What is the isolation voltage rating of SI86S640BC-AS1R and which safety standards does it meet?
The SI86S640BC-AS1R has a 6000 VRMS isolation rating for 1 minute per UL 1577 and is certified to VDE 60747-17 (reinforced insulation), CSA 62368-1, and CQC GB4943.1. These approvals validate its use in safety-critical systems such as EV onboard chargers and medical power supplies where reinforced barrier integrity is mandated.
Does SI86S640BC-AS1R require external initialization or configuration after power-up?
No, SI86S640BC-AS1R requires no start-up initialization due to its RF-modulated isolation architecture. Outputs become valid within 0.3 ms of VDD crossing the UVLO threshold (2.18 V typical), and the device enters normal operation without firmware or register writes-critical for fail-safe systems like battery management.
What is the function of the EN1 and EN2 pins on SI86S640BC-AS1R?
EN1 and EN2 are active-high enable inputs that place all outputs on Side A and Side B, respectively, into high-impedance state. This allows multiple SI86S640BC-AS1R devices to share a common isolated bus or enables dynamic power gating in low-power modes without disrupting signal integrity.
How does the fail-safe default-low feature operate in SI86S640BC-AS1R during power loss?
When VDD1 drops below 2.25 V while VDD2 remains powered, SI86S640BC-AS1R's outputs on Side B default to logic low-guaranteeing a known safe state. This behavior is factory-configured and eliminates risk of undefined outputs during MCU brownout in traction inverter control or BMS fault handling.
Is SI86S640BC-AS1R compatible with 3.3 V and 5 V logic families on both sides simultaneously?
Yes, SI86S640BC-AS1R supports independent 2.25–5.5 V supplies on Side A (VDD1) and Side B (VDD2), enabling direct interfacing with 3.3 V microcontrollers on one side and 5 V analog front-ends or gate drivers on the other-no external level shifters required.
SI86S640BC-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 4/0
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 42ns, 42ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86S640BC-AS1R FAQ
1.How can I place an order for SI86S640BC-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86S640BC-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86S640BC-AS1R reliable?
The price and inventory of SI86S640BC-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86S640BC-AS1R is usually 5 days.
3.What payment methods are accepted for SI86S640BC-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86S640BC-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86S640BC-AS1R?
SI86S640BC-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86S640BC-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86S640BC-AS1R?
For technical support, including SI86S640BC-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86S640BC-AS1R requirements.
6.How does Aetrix verify that SI86S640BC-AS1R is sourced from the original manufacturer or authorized distributors?
All SI86S640BC-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86S640BC-AS1R meets industry standards.
7.What is the process for return or replacement of SI86S640BC-AS1R?
All SI86S640BC-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI86S640BC-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86S640BC-AS1R part is unused and in its original packaging.
Return procedure for SI86S640BC-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86S640BC-AS1R Tags
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ISO1212DBQR
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ISO6721BDR
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SI8710AC-B-ISR
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ISO7720FDR
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ISO7721DR
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SI8710CC-B-ISR
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ISO6741FQDWRQ1
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ISO7721DWVR
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ISO7762FDBQR
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ISO7741DWR
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ISO7741FDWR
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