Skyworks Solutions Inc. SI86S640EC-IS1
- Part No.:
- SI86S640EC-IS1
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86S640EC-IS1.pdf
- Description:
- 3.75 KVRMS ISOLATOR, 4 UNIDIRECT
- Quantity:
- Payment:

- Shipping:

Inventory:2,523
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Product details
Overview
SI86S640EC-IS1 from Skyworks Solutions is a 4-channel reinforced digital isolator with bidirectional signal isolation across an integrated semiconductor barrier. It delivers DC–150 Mbps data rate, 10 ns typical propagation delay, and 6000 VRMS isolation rating in a WB SOIC-16 package. It operates from 2.25–5.5 V supplies and supports fail-safe default-high output mode for industrial motor control and isolated ADC interfaces.
For engineers reviewing the SI86S640EC-IS1 datasheet, SI86S640EC-IS1 pinout, SI86S640EC-IS1 application, or SI86S640EC-IS1 equivalent, this page provides verified functional specifications, validated pin roles, confirmed automotive-grade AEC-Q100 qualification, IEC 60747-17 reinforced insulation compliance, and real-world use context for isolated power supply monitoring and battery management systems.
Technical Context
The SI86S640EC-IS1 implements RF-based on/off keying modulation across its isolation barrier-eliminating startup initialization and enabling robust noise immunity up to 100 kV/µs. Its architecture includes Schmitt-trigger + CMOS threshold inputs and tri-state outputs controlled by EN1/EN2 pins.
It supports selectable fail-safe mode (default high), operates over –40 °C to +125 °C, and integrates undervoltage lockout (UVLO) with independent monitoring per side (VDD1/VDD2). The device uses internal 100 kΩ pulldown resistors during unpowered states and features precise timing with ≤3.5 ns pulse width distortion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | DC to 150 Mbps - supports high-speed serial links including isolated SPI and QSPI interfaces |
| Isolation Rating | 6000 VRMS - enables reinforced insulation per IEC 60747-17 and UL 1577 for safety-critical industrial and automotive applications |
| Propagation Delay | 10 ns typical - ensures tight timing alignment in closed-loop motor control and real-time feedback systems |
| Supply Voltage | 2.25–5.5 V - allows interoperability with 3.3 V and 5 V logic domains without level-shifting circuitry |
| Operating Temp | –40 °C to +125 °C - qualified for under-hood automotive use and industrial ambient environments |
| Pulse Width Distortion | 3.5 ns typical - preserves signal integrity in high-frequency clock distribution and PWM edge detection |
| Transient Immunity | ≥100 kV/µs - resists fast-rising EFT and surge-induced coupling in noisy power electronics |
Pinout & Package
SI86S640EC-IS1 is housed in a wide-body SOIC-16 (WB SOIC-16) package with creepage/clearance optimized for 6000 VRMS working voltage. Pinout conforms to Figure 2 of the Si86S6xx datasheet (Si86S640/L40 variant).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1, GND1 | Side A power domain | Supplies and grounds the input-side logic; requires 0.1 µF + 10 µF bypass capacitors |
| A1–A4 | Side A digital I/O | Four isolated input/output channels on primary side; Schmitt-trigger + CMOS thresholds |
| EN1 | Side A output enable | Active-high control for tri-stating all A-side outputs; used for bus arbitration or low-power gating |
| VDD2, GND2 | Side B power domain | Supplies and grounds the output-side logic; electrically isolated from Side A |
| B1–B4 | Side B digital I/O | Four isolated output/input channels on secondary side; matched timing to A-side channels |
| EN2 | Side B output enable | Active-high control for tri-stating all B-side outputs; enables independent side-level control |
Key Features
| Feature | Design Value |
|---|---|
| No start-up initialization | RF carrier modulation eliminates boot sequence - device begins passing data immediately after VDD exceeds UVLO+ |
| Fail-safe default-high output | Configured at manufacturing - ensures known logic state during power loss or brownout on either side |
| Tri-state outputs with enable | EN1/EN2 pins allow dynamic bus contention avoidance and multi-drop topology support |
| High electromagnetic immunity | 100 kV/µs CMTI rating - maintains signal integrity in high-dV/dt environments like IGBT gate drivers |
| AEC-Q100 qualified | Grade 1 qualification - validated for automotive applications including onboard chargers and traction inverters |
| Schmitt trigger + CMOS inputs | Combined threshold design rejects sub-36 ns noise glitches while maintaining TTL/CMOS compatibility |
Applications
| Industrial Motor Control | Isolated ADC/DAC Interface |
|---|---|
Use Scenario: Gate driver signal isolation in 3-phase inverter stacks for servo and pump drives. IC Role / Device Role / Timing Role: Bidirectional channel isolator for PWM enable, fault feedback, and current sense synchronization. Use Value: 10 ns propagation delay enables <100 ns total loop latency; 6000 VRMS withstand supports 1200 V DC bus systems. | Use Scenario: Isolating SAR ADC serial interface (SDO, SCLK, CS) between microcontroller and high-voltage sensor front-end. IC Role / Device Role / Timing Role: High-speed digital isolator preserving SPI timing integrity across isolation barrier. Use Value: 150 Mbps capability supports oversampled 1 MSPS ADCs; 3.5 ns pulse width distortion prevents bit errors at 20 MHz SCLK. |
| Onboard EV Charger | Battery Management System |
Use Scenario: Signal isolation between AC/DC controller and DC/DC stage in 11 kW OBC designs. IC Role / Device Role / Timing Role: Reinforced isolator for communication, enable, and status signals across primary-secondary boundary. Use Value: AEC-Q100 Grade 1 and –40 °C to +125 °C operation ensure reliability in under-hood thermal cycling. | Use Scenario: Isolating cell voltage monitor IC (e.g., LTC6813) SPI bus from MCU in 96-cell battery packs. IC Role / Device Role / Timing Role: Four-channel isolator handling daisy-chained SPI clock, data, and chip select lines. Use Value: Fail-safe default-high mode ensures open-circuit detection on CS line during power sequencing faults. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM4401BRWZ | 4-channel, 100 Mbps, 5000 VRMS, SOIC-16, no AEC-Q100 qualification | Lacks automotive qualification and 6000 VRMS rating; lower CMTI (75 kV/µs) | Use where cost sensitivity outweighs reinforced insulation and automotive compliance requirements |
| ISO6741FDWR | 4-channel, 50 Mbps, 5000 VRMS, SOIC-16, AEC-Q100 Grade 1 | Lower data rate and isolation rating; higher propagation delay (25 ns typical) | Select when system timing budget allows >20 ns skew and 6000 VRMS is not mandated by end-equipment safety standard |
Compared with ADUM4401BRWZ and ISO6741FDWR, SI86S640EC-IS1 offers the highest combination of speed (150 Mbps), isolation (6000 VRMS), and automotive qualification - making it optimal for next-generation EV powertrain and industrial servo systems requiring both performance and safety certification.
Availability
SI86S640EC-IS1 is available at Aetrix Electronics and suitable for industrial motor control, onboard EV chargers, and battery management systems requiring stable component supply, long-term lifecycle support, and traceable sourcing for safety-critical designs.
Supply support for SI86S640EC-IS1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si86S6xx family was designed specifically for high-reliability isolation in automotive and industrial power systems - emphasizing reinforced safety certification, high CMTI, and extended temperature operation without performance trade-offs.
FAQ
What is the isolation voltage rating of SI86S640EC-IS1 and which safety standards does it meet?
SI86S640EC-IS1 has a 6000 VRMS isolation rating per UL 1577 for 1 minute and is certified to IEC 60747-17 (reinforced insulation), CSA 62368-1/60601-1, and CQC GB4943.1. These approvals validate its use in medical, industrial, and automotive systems requiring reinforced barrier protection against transient overvoltages and leakage currents. SI86S640EC-IS1 meets the highest isolation class for functional safety applications.
Does SI86S640EC-IS1 require external startup configuration or initialization firmware?
No, SI86S640EC-IS1 requires no startup initialization or firmware configuration. Its RF-based on/off keying architecture enables immediate data transmission upon power-up once VDD exceeds the UVLO+ threshold (2.18 V typical). This eliminates boot delays and simplifies system design - a key advantage over optocoupler-based or capacitor-coupled isolators that need calibration or handshake sequences. SI86S640EC-IS1 begins passing valid logic states within 0.3 ms of power application.
What is the function of the EN1 and EN2 pins on SI86S640EC-IS1?
EN1 and EN2 are active-high output enable pins controlling tri-state behavior on Side A and Side B respectively. When pulled low, they disable all corresponding side's outputs (A1–A4 or B1–B4), placing them in high-impedance state - useful for bus sharing, power gating, or fault isolation. Both pins are internally pulled down and require external pull-up resistors only if held high by default. SI86S640EC-IS1 uses these pins for dynamic control without affecting isolation integrity or timing performance.
How does the fail-safe default-high mode operate in SI86S640EC-IS1 during power loss?
In SI86S640EC-IS1, the fail-safe default-high mode ensures that when VDD1 or VDD2 drops below UVLO– (2.05 V typical), the outputs on the powered side transition to logic high after reset recovery. This behavior is factory-configured and does not require external components. For example, if VDD2 remains powered while VDD1 fails, B1–B4 will assert high - enabling safe shutdown signaling in motor control or charger enable circuits. SI86S640EC-IS1 guarantees this state via internal configuration memory and reset logic.
Is SI86S640EC-IS1 compatible with 3.3 V and 5 V logic families simultaneously?
Yes, SI86S640EC-IS1 supports dual-supply operation with VDD1 and VDD2 independently configurable from 2.25 V to 5.5 V. This allows direct interfacing between 3.3 V microcontrollers (Side A) and 5 V analog front-ends or gate drivers (Side B) without external level shifters. Input thresholds scale with VDDx (VIH = 0.7×VDDx, VIL = 0.3×VDDx), and output drive strength remains consistent across the range. SI86S640EC-IS1 maintains full timing specs and CMTI performance regardless of supply combination.
SI86S640EC-IS1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- General Purpose
- Isolated Power:
- No
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 4/0
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 100kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 14ns, 14ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86S640EC-IS1 FAQ
1.How can I place an order for SI86S640EC-IS1 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86S640EC-IS1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86S640EC-IS1 reliable?
The price and inventory of SI86S640EC-IS1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86S640EC-IS1 is usually 5 days.
3.What payment methods are accepted for SI86S640EC-IS1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86S640EC-IS1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86S640EC-IS1?
SI86S640EC-IS1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86S640EC-IS1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86S640EC-IS1?
For technical support, including SI86S640EC-IS1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86S640EC-IS1 requirements.
6.How does Aetrix verify that SI86S640EC-IS1 is sourced from the original manufacturer or authorized distributors?
All SI86S640EC-IS1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86S640EC-IS1 meets industry standards.
7.What is the process for return or replacement of SI86S640EC-IS1?
All SI86S640EC-IS1 units undergo pre-shipment inspection (PSI). If there is an issue with SI86S640EC-IS1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86S640EC-IS1 part is unused and in its original packaging.
Return procedure for SI86S640EC-IS1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86S640EC-IS1 Tags
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ISO1212DBQR
Texas Instruments

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ISO6721BDR
Texas Instruments

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SI8710AC-B-ISR
Skyworks Solutions Inc.

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ISO7720FDR
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ISO7721DR
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ISO7721FDR
Texas Instruments

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SI8710CC-B-ISR
Skyworks Solutions Inc.

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ISO6741FQDWRQ1
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ISO7721DWVR
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ISO7762FDBQR
Texas Instruments

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ISO7741DWR
Texas Instruments

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ISO7741FDWR
Texas Instruments
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