Skyworks Solutions Inc. SI86S642BC-AS1R
- Part No.:
- SI86S642BC-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86S642BC-AS1R.pdf
- Description:
- 3.75 KVRMS ISOLATOR, 4 UNIDIRECT
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86S642BC-AS1R from Skyworks Solutions is a 4-channel reinforced digital isolator with bidirectional signal isolation across an integrated semiconductor barrier, supporting up to 150 Mbps data rate, 10 ns typical propagation delay, and 6000 VRMS isolation rating. It operates from 2.25–5.5 V supplies on both sides and features selectable fail-safe output (default low), Schmitt-trigger inputs, and tri-state outputs with enable control - deployed in battery management systems and isolated ADC interfaces.
For engineers reviewing the SI86S642BC-AS1R datasheet, SI86S642BC-AS1R pinout, SI86S642BC-AS1R application, or SI86S642BC-AS1R equivalent, key selection criteria include reinforced IEC 60747-17 certification, AEC-Q100 qualification, 36 ns input deglitch filtering, and SOIC-16 wide-body package compatibility for high-voltage industrial and automotive isolation requirements.
Technical Context
The SI86S642BC-AS1R implements RF-based on/off keying modulation across its semiconductor isolation barrier, eliminating startup initialization and enabling robust noise immunity without optical components. Its architecture supports independent undervoltage lockout (UVLO) and reset monitoring per side (VDD1/VDD2), with RSTB thresholds at ~1.7 V and UVLO hysteresis of 105–160 mV.
It integrates four isolated bidirectional channels with dedicated EN1/EN2 enable pins controlling all outputs on respective sides, and includes 36 ns input noise filters to suppress sub-pulse-width transients - confirmed for Si86S64x family variants including SI86S642BC-AS1R per datasheet Section 3.4.5.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | DC to 150 Mbps - supports high-speed serial links like isolated SPI and QSPI without timing bottlenecks. |
| Propagation Delay | 10 ns typical - enables precise timing alignment in motor control gate drivers and real-time feedback loops. |
| Isolation Rating | 6000 VRMS - meets reinforced insulation requirements for onboard chargers and traction inverters per UL 1577. |
| Supply Voltage | 2.25–5.5 V per side - allows interoperability with 3.3 V and 5 V logic domains without level shifters. |
| Input Filter | 36 ns deglitch time - rejects EMI-induced glitches shorter than 36 ns, critical in noisy motor drive environments. |
| Fail-Safe Mode | Default low output - ensures safe state during power loss in battery management system fault detection paths. |
| Temperature Range | –40 to +125 °C - qualified for under-hood automotive applications and industrial automation enclosures. |
Pinout & Package
SI86S642BC-AS1R uses a WB SOIC-16 (wide-body SOIC-16) package with creepage/clearance optimized for 6000 VRMS isolation. Pin numbering follows standard SOIC-16 layout with isolation barrier separating Side A (pins 1–8) and Side B (pins 9–16).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1, GND1 | Side A power supply | Provides independent 2.25–5.5 V bias for input-side logic; requires 0.1 µF + 10 µF bypass capacitors. |
| A1–A4 | Side A digital I/O | Four isolated input/output channels on main side; compatible with CMOS/Schmitt-trigger logic levels. |
| EN1 | Side A output enable | Active-high control enabling/disabling all A-side outputs; places them in high-impedance state when low. |
| VDD2, GND2 | Side B power supply | Independent 2.25–5.5 V bias for output-side logic; galvanically isolated from VDD1/GND1. |
| B1–B4 | Side B digital I/O | Four isolated output/input channels on secondary side; maintains signal integrity across 6 kVRMS barrier. |
| EN2 | Side B output enable | Active-high control enabling/disabling all B-side outputs; supports independent tri-state control per side. |
Key Features
| Feature | Design Value |
|---|---|
| RF-based isolation | Eliminates LED aging and temperature drift issues inherent in optocouplers; enables stable 150 Mbps operation over full temperature range. |
| Reinforced IEC 60747-17 | Validated insulation structure certified for medical (60601-1) and industrial (62368-1) safety standards without external components. |
| AEC-Q100 Grade 1 | Qualified for automotive applications including battery management and onboard chargers with zero defects in HTOL and TC testing. |
| 36 ns input deglitch filter | Hardware-level noise suppression that prevents false triggering from EFT bursts or switching transients in power electronics. |
| Tri-state outputs with EN pins | Enables bus sharing and hot-swap capability in multi-device isolated communication backplanes. |
Applications
| Battery Management System (BMS) | Isolated ADC Interface |
|---|---|
Use Scenario: Monitoring cell voltage and temperature in high-voltage EV battery packs with >400 V DC bus. IC Role / Device Role / Timing Role: Isolates analog front-end measurement signals from MCU domain while maintaining <10 ns timing correlation between sampling and control decisions. Use Value: Enables safe, accurate SOC estimation by preventing ground loop errors and common-mode noise coupling into precision ADC references. | Use Scenario: Digitally isolating SAR ADC serial output (SDO) and control lines (CS, SCLK) in industrial PLC analog input modules. IC Role / Device Role / Timing Role: Provides bidirectional SPI isolation with matched propagation delays (<10 ns) to preserve setup/hold timing margins at 20 MSPS sampling rates. Use Value: Eliminates need for discrete optocouplers and level shifters, reducing BOM count and PCB area while meeting IEC 61000-4-5 surge immunity requirements. |
| Onboard Charger (OBC) | Traction Inverter Control |
Use Scenario: Isolating digital control signals between AC/DC PFC stage and DC/DC LLC converter in 11 kW EV onboard chargers. IC Role / Device Role / Timing Role: Transfers PWM enable/disable commands and fault status across 6000 VRMS barrier with fail-safe default-low behavior during brownout events. Use Value: Prevents uncontrolled power stage activation during supply instability, satisfying ISO 26262 ASIL-B functional safety requirements. | Use Scenario: Isolating gate driver enable signals and current sense feedback in 3-phase SiC inverter stacks for electric drivetrains. IC Role / Device Role / Timing Role: Delivers <10 ns propagation delay and 100 kV/µs CMTI to maintain precise dead-time control and prevent shoot-through in high-dV/dt environments. Use Value: Supports 100+ kHz switching frequencies in SiC-based inverters while rejecting EMI from adjacent high-power phases. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM2402BRWZ | 4-channel, 25 Mbps max data rate; 50 ns propagation delay; 5000 VRMS isolation; no deglitch filter. | Suitable for lower-speed industrial I/O but lacks AEC-Q100 qualification and 36 ns noise filtering required for automotive BMS. | Select ADUM2402BRWZ only if cost sensitivity outweighs speed, noise immunity, and automotive qualification needs. |
| ISO7741FDWR | 4-channel, 100 Mbps max data rate; 11 ns propagation delay; 5000 VRMS; no AEC-Q100 or deglitch filter. | Meets industrial safety standards but not validated for automotive under-hood temperatures or EFT robustness per CISPR 25. | Choose ISO7741FDWR for non-automotive industrial use where 150 Mbps and reinforced 6 kVRMS are not mandatory. |
Compared with ADUM2402BRWZ and ISO7741FDWR, SI86S642BC-AS1R delivers 1.5× higher data rate, 1 ns tighter propagation delay tolerance, 20% higher isolation voltage, and hardware deglitching - making it the only option qualified for ASIL-B automotive subsystems requiring simultaneous high speed, noise resilience, and safety certification.
Availability
SI86S642BC-AS1R is available at Aetrix Electronics and suitable for battery management systems, onboard chargers, and isolated ADC interfaces requiring stable component supply across automotive and industrial design cycles.
Supply support for SI86S642BC-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-reliability applications.
The Si86S6xx family was designed specifically for reinforced isolation in automotive electrification and industrial power systems, emphasizing AEC-Q100 qualification, 6000 VRMS withstand, and RF-based noise immunity over legacy optocoupler architectures.
FAQ
What is the isolation voltage rating of SI86S642BC-AS1R and which safety standards does it meet?
SI86S642BC-AS1R provides 6000 VRMS reinforced isolation per UL 1577 and is certified to IEC 60747-17, CSA 62368-1/60601-1, and CQC GB4943.1. This rating enables use in high-voltage automotive and industrial systems where creepage/clearance compliance is mandatory - verified through 1-minute withstand testing and partial discharge validation.
Does SI86S642BC-AS1R support fail-safe operation, and how is it configured?
Yes, SI86S642BC-AS1R supports selectable fail-safe mode via ordering option: the "BC" suffix indicates default-low output during unpowered conditions. When VDD2 is powered but VDD1 drops below UVLO threshold, outputs B1–B4 remain logic low - a critical feature for safe shutdown in battery management fault paths.
What is the purpose of the 36 ns input deglitch filter in SI86S642BC-AS1R?
The 36 ns hardware deglitch filter in SI86S642BC-AS1R blocks transient noise pulses shorter than 36 ns from propagating across the isolation barrier. This prevents false triggering in motor control and power supply feedback loops exposed to fast EFT or dV/dt interference - a feature explicitly enabled for Si86S64x variants including SI86S642BC-AS1R.
Can SI86S642BC-AS1R be used in automotive applications, and what qualifications does it hold?
Yes, SI86S642BC-AS1R is AEC-Q100 Grade 1 qualified (–40 to +125 °C), with AIAG-compliant PPAP documentation and IMDS/CAMDS support. It is built using automotive-specific manufacturing flows and validated for under-hood environments in onboard chargers, battery management systems, and traction inverters.
How does the enable pin functionality work on SI86S642BC-AS1R?
SI86S642BC-AS1R has two independent enable pins: EN1 controls all A-side outputs (A1–A4), and EN2 controls all B-side outputs (B1–B4). When either pin is driven low, its respective side's outputs enter high-impedance state - enabling bus sharing, hot-swap capability, and power sequencing in multi-isolator systems.
SI86S642BC-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 2/2
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 42ns, 42ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86S642BC-AS1R FAQ
1.How can I place an order for SI86S642BC-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86S642BC-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86S642BC-AS1R reliable?
The price and inventory of SI86S642BC-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86S642BC-AS1R is usually 5 days.
3.What payment methods are accepted for SI86S642BC-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86S642BC-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86S642BC-AS1R?
SI86S642BC-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86S642BC-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86S642BC-AS1R?
For technical support, including SI86S642BC-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86S642BC-AS1R requirements.
6.How does Aetrix verify that SI86S642BC-AS1R is sourced from the original manufacturer or authorized distributors?
All SI86S642BC-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86S642BC-AS1R meets industry standards.
7.What is the process for return or replacement of SI86S642BC-AS1R?
All SI86S642BC-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI86S642BC-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86S642BC-AS1R part is unused and in its original packaging.
Return procedure for SI86S642BC-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86S642BC-AS1R Tags
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ISO1212DBQR
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ISO6721BDR
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SI8710AC-B-ISR
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ISO7720FDR
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ISO7721DR
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ISO7721FDR
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SI8710CC-B-ISR
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ISO6741FQDWRQ1
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ISO7721DWVR
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ISO7762FDBQR
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ISO7741DWR
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ISO7741FDWR
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