Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Isolators > Digital Isolators

Skyworks Solutions Inc. SI86S642HE-AS2

Name: SI86S642HE-AS2
Brand: Skyworks Solutions Inc.
SKU: SI86S642HE-AS2
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI86S642HE-AS2

Manufacturer:: Skyworks Solutions Inc.

Category:: Digital Isolators

Package:: 16-SOIC (0.295", 7.50mm Width)

Datasheet:: SI86S642HE-AS2.pdf

Description:: 6.0 KVRMS ISOLATOR, 4 UNIDIRECTI

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,830

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI86S642HE-AS2 from Skyworks Solutions is a 4-channel reinforced digital isolator with bidirectional signal isolation across an integrated semiconductor barrier, supporting up to 150 Mbps data rate, 10 ns typical propagation delay, and 6000 VRMS isolation rating. It operates from 2.25–5.5 V on both sides and features Schmitt-trigger + CMOS inputs, tri-state outputs with enable, and selectable fail-safe output (default high or low) for industrial motor control and battery management systems.

For engineers reviewing the SI86S642HE-AS2 datasheet, SI86S642HE-AS2 pinout, SI86S642HE-AS2 application, or SI86S642HE-AS2 equivalent, key selection criteria include its 4-channel A/B I/O configuration, WB SOIC-16 package with 8.3 mm creepage, reinforced IEC 60747-17 certification, and support for fail-safe mode selection via ordering code - all critical for isolated ADC interfaces and traction inverter gate driver supervision.

Technical Context

The SI86S642HE-AS2 implements RF-based on/off keying modulation across a monolithic silicon dioxide isolation barrier, eliminating startup initialization and enabling deterministic timing behavior. Its architecture delivers 3.5 ns typical pulse width distortion and 100 kV/µs common-mode transient immunity (CMTI), with independent UVLO and reset circuitry per side (VDD1/VDD2) ensuring robust operation during supply transients.

It supports dual-supply operation with side-specific enable pins (EN1/EN2), tri-state output control, and failsafe output state selection determined at manufacture - not configurable in-circuit. The device includes input deglitch filtering (36 ns) and operates across –40 °C to +125 °C ambient, meeting AEC-Q100 Grade 1 requirements for automotive onboard chargers and BMS.

Key Specifications

Parameter	Value and Actual Design Meaning
Data Rate	DC to 150 Mbps - enables high-speed SPI, isolated ADC sampling, and real-time feedback loops without protocol translation.
Propagation Delay	10 ns typical - ensures tight timing alignment between controller and isolated power stage, critical for PWM synchronization.
Isolation Rating	6000 VRMS (1 min) - meets reinforced insulation requirements for 1000 VAC industrial bus interfaces and EV traction inverters.
Supply Voltage	2.25–5.5 V per side - allows direct interfacing with 3.3 V microcontrollers and 5 V analog front-ends without level shifters.
CMTI	≥100 kV/µs - prevents false triggering in high-dV/dt environments like IGBT gate drivers and motor phase legs.
Operating Temp	–40 °C to +125 °C - qualified for under-hood automotive use and industrial variable-frequency drives.
Fail-Safe Mode	Default high-output (HE suffix) - ensures gate driver disable or fault flag assertion during VDD1 loss in safety-critical paths.

Pinout & Package

SI86S642HE-AS2 is housed in a wide-body SOIC-16 (WB SOIC-16) package with 10.3 mm body width, 8.3 mm creepage, and reinforced insulation barrier. Pin numbering follows standard SOIC layout (pin 1 = VDD1, pin 16 = VDD2), with 8-channel I/O split across two isolated sides.

Pin/Terminal	Circuit Role	Design Meaning
VDD1, GND1	Side A power supply	Provides bias for A-side transmitter circuits; requires 0.1 µF + 10 µF local bypassing.
A1–A4	Side A digital I/O	Four unidirectional input channels from controller side; accept CMOS/Schmitt thresholds (VIH ≥ 0.7×VDD1).
EN1	Side A output enable	Active-high control: drives A-side outputs into high-impedance when low - used for bus arbitration or power sequencing.
Isolation Barrier	Internal SiO₂ dielectric	Monolithic semiconductor barrier rated for 6000 VRMS withstand; no external components required for isolation integrity.
B1–B4	Side B digital I/O	Four isolated output channels to power stage or sensor side; VOH ≥ VDD2–0.4 V at –4 mA load.
EN2	Side B output enable	Active-high control: places B-side outputs in tri-state - enables shared-bus topologies on isolated side.
VDD2, GND2	Side B power supply	Independent bias for B-side receiver circuits; supports separate 3.3 V/5 V domains with no ground loop.

Key Features

Feature	Design Value
No start-up initialization	RF carrier modulation eliminates boot sequence - outputs follow inputs within 0.3 ms of VDD stabilization, avoiding system lockup.
Selectable fail-safe output	HE suffix denotes default-high output during VDD1 loss - asserts active-low fault signals or disables gate drivers by design.
Input deglitch filter	36 ns pulse rejection - suppresses EMI-induced spikes on motor current sense lines without affecting 150 Mbps data integrity.
Tri-state outputs with EN	Dual enable pins (EN1/EN2) allow independent side-level bus contention control - essential for multi-master isolated SPI buses.
Reinforced IEC 60747-17	Qualified for functional safety applications requiring dual insulation barriers - accepted for IEC 62368-1 and IEC 60601-1 end-equipment certification.

Applications

Motor Control Feedback	Isolated ADC Interface
Use Scenario: Real-time current/voltage sensing in 3-phase inverter legs using shunt resistors and isolated sigma-delta modulators. IC Role / Device Role / Timing Role: Isolates digital bitstream from modulator to MCU while preserving timing integrity for closed-loop current regulation. Use Value: 10 ns propagation delay and 3.5 ns pulse width distortion enable <100 ns total loop latency - sufficient for 20 kHz PWM switching with overcurrent protection.	Use Scenario: Connecting isolated 24-bit ADCs (e.g., AD7403) to host processors in medical imaging power supplies. IC Role / Device Role / Timing Role: Transfers serial bitstream across isolation barrier with deterministic jitter <1 ns RMS - preserves ENOB in precision measurement paths. Use Value: 150 Mbps capability supports 20 MSPS ADC sampling with 8x oversampling, eliminating need for parallel isolation or FPGA glue logic.
Onboard Charger Supervision	Traction Inverter Gate Driver Interface
Use Scenario: Monitoring DC-link voltage, coolant temperature, and contactor status in EV onboard chargers. IC Role / Device Role / Timing Role: Provides fail-safe isolated digital inputs to MCU; HE suffix ensures open-circuit detection defaults to "charger disabled" state. Use Value: Default-high output during VDD1 loss prevents unintended charging activation - satisfies ISO 6469-3 functional safety requirement for HV interlock monitoring.	Use Scenario: Transmitting PWM signals and fault acknowledgments between MCU and isolated gate driver ICs (e.g., Si823Hx) in 800 V traction inverters. IC Role / Device Role / Timing Role: Delivers <10 ns channel-to-channel skew and >100 kV/µs CMTI to prevent shoot-through during high-dV/dt switching transitions. Use Value: Enables 10 kHz–20 kHz switching frequencies with <50 ns dead-time margin - directly supporting SiC MOSFET gate drive timing budgets.

Motor Control Feedback

Isolated ADC Interface

Use Scenario: Real-time current/voltage sensing in 3-phase inverter legs using shunt resistors and isolated sigma-delta modulators.

IC Role / Device Role / Timing Role: Isolates digital bitstream from modulator to MCU while preserving timing integrity for closed-loop current regulation.

Use Value: 10 ns propagation delay and 3.5 ns pulse width distortion enable <100 ns total loop latency - sufficient for 20 kHz PWM switching with overcurrent protection.

Use Scenario: Connecting isolated 24-bit ADCs (e.g., AD7403) to host processors in medical imaging power supplies.

IC Role / Device Role / Timing Role: Transfers serial bitstream across isolation barrier with deterministic jitter <1 ns RMS - preserves ENOB in precision measurement paths.

Use Value: 150 Mbps capability supports 20 MSPS ADC sampling with 8x oversampling, eliminating need for parallel isolation or FPGA glue logic.

Onboard Charger Supervision

Traction Inverter Gate Driver Interface

Use Scenario: Monitoring DC-link voltage, coolant temperature, and contactor status in EV onboard chargers.

IC Role / Device Role / Timing Role: Provides fail-safe isolated digital inputs to MCU; HE suffix ensures open-circuit detection defaults to "charger disabled" state.

Use Value: Default-high output during VDD1 loss prevents unintended charging activation - satisfies ISO 6469-3 functional safety requirement for HV interlock monitoring.

Use Scenario: Transmitting PWM signals and fault acknowledgments between MCU and isolated gate driver ICs (e.g., Si823Hx) in 800 V traction inverters.

IC Role / Device Role / Timing Role: Delivers <10 ns channel-to-channel skew and >100 kV/µs CMTI to prevent shoot-through during high-dV/dt switching transitions.

Use Value: Enables 10 kHz–20 kHz switching frequencies with <50 ns dead-time margin - directly supporting SiC MOSFET gate drive timing budgets.

Equivalent & Alternatives

The following parts are listed as comparable options for similar digital isolator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADUM4402BRWZ	4-channel, 100 Mbps, 5000 VRMS, SOIC-16, default-low fail-safe	Lacks 6000 VRMS rating and AEC-Q100 qualification; lower CMTI (75 kV/µs)	Acceptable for non-automotive industrial PLC I/O where 5 kVRMS suffices and default-low behavior aligns with system logic.
ISO6741FDWR	4-channel, 50 Mbps, 5000 VRMS, SOIC-16, no fail-safe selection option	Lower data rate limits SPI clock speed to ≤12.5 MHz; no deglitch filter or sleep mode	Suitable for cost-sensitive battery monitor BMS where 50 Mbps covers UART telemetry and thermal sensor polling only.

Compared with ADUM4402BRWZ and ISO6741FDWR, SI86S642HE-AS2 provides higher isolation voltage, automotive qualification, and configurable fail-safe state - making it the only choice for ISO 26262 ASIL-B compliant traction inverter supervision and 150 Mbps isolated data acquisition.

Availability

SI86S642HE-AS2 is available at Aetrix Electronics and suitable for industrial motor control, EV onboard chargers, and isolated ADC interfaces requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for safety-critical designs.

Supply support for SI86S642HE-AS2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-reliability applications.

The Si86S6xx family was designed specifically for high-speed, reinforced isolation in automotive and industrial power systems - emphasizing CMTI performance, fail-safe behavior, and AEC-Q100 compliance from wafer fabrication through final test.

FAQ

What is the isolation voltage rating of SI86S642HE-AS2 and which safety standards does it meet?

SI86S642HE-AS2 is rated for 6000 VRMS isolation for 1 minute per UL 1577 and carries reinforced insulation certification per IEC 60747-17. It also meets CSA 62368-1 and 60601-1, and CQC GB4943.1 - enabling use in medical power supplies and EV traction inverters requiring double insulation without additional external barriers.

Does SI86S642HE-AS2 require external components for basic operation?

SI86S642HE-AS2 requires only two bypass capacitors per side: 0.1 µF ceramic and 10 µF bulk capacitor placed near VDD1/GND1 and VDD2/GND2. No pull-up/down resistors, level shifters, or initialization firmware are needed - the device begins passing data within 0.3 ms of VDD stabilization.

How does the HE suffix in SI86S642HE-AS2 affect its behavior during power loss?

The HE suffix indicates a factory-configured default-high fail-safe mode. When VDD1 drops below UVLO threshold while VDD2 remains powered, all B1–B4 outputs transition to logic high - enabling safe shutdown of gate drivers or assertion of fault flags in safety-critical power stages without external supervision circuitry.

Can SI86S642HE-AS2 support bidirectional communication on individual channels?

No - SI86S642HE-AS2 has four unidirectional channels (A1→B1, A2→B2, A3→B3, A4→B4). For bidirectional data flow, such as SPI full-duplex, designers must pair it with a complementary reverse-channel isolator or select the Si86SQ44 QSPI variant with direction control.

What is the purpose of the 36 ns input deglitch filter in SI86S642HE-AS2?

The 36 ns deglitch filter rejects narrow noise pulses (<36 ns width) induced by switching transients or ESD events on A1–A4 inputs - preventing false edge detection in motor current sensing or contactor status monitoring while preserving full 150 Mbps data throughput for valid signals.

SI86S642HE-AS2 Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 16-SOIC (0.295", 7.50mm Width)

Packaging:: Tube

Product Status:: Active

Technology:: Capacitive Coupling

Type:: SPI

Isolated Power:: Yes

Number of Channels:: 4

Inputs - Side 1/Side 2:: 2/2

Channel Type:: Unidirectional

Voltage - Isolation:: 6000Vrms

Common Mode Transient Immunity (Min):: 150kV/µs

Data Rate:: 150Mbps

Propagation Delay tpLH / tpHL (Max):: 42ns, 42ns

Pulse Width Distortion (Max):: 2ns

Rise / Fall Time (Typ):: 2.5ns, 2.5ns

Voltage - Supply:: 2.25V ~ 5.5V

Grade:: Automotive

Qualification:: AEC-Q100

Operating Temperature:: -40°C ~ 125°C

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

SI86S642HE-AS2 FAQ

1.How can I place an order for SI86S642HE-AS2 through Aetrix?

Please submit a Request for Quotation (RFQ) for SI86S642HE-AS2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI86S642HE-AS2 reliable?

The price and inventory of SI86S642HE-AS2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86S642HE-AS2 is usually 5 days.

3.What payment methods are accepted for SI86S642HE-AS2?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86S642HE-AS2 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI86S642HE-AS2?

SI86S642HE-AS2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI86S642HE-AS2 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI86S642HE-AS2?

For technical support, including SI86S642HE-AS2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86S642HE-AS2 requirements.

6.How does Aetrix verify that SI86S642HE-AS2 is sourced from the original manufacturer or authorized distributors?

All SI86S642HE-AS2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86S642HE-AS2 meets industry standards.

7.What is the process for return or replacement of SI86S642HE-AS2?

All SI86S642HE-AS2 units undergo pre-shipment inspection (PSI). If there is an issue with SI86S642HE-AS2, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI86S642HE-AS2 part is unused and in its original packaging.

Return procedure for SI86S642HE-AS2:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…