Skyworks Solutions Inc. SI86S662EB-AUR
- Part No.:
- SI86S662EB-AUR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
SI86S662EB-AUR.pdf
- Description:
- 2.5 KVRMS ISOLATOR, 6 UNIDIRECTI
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86S662EB-AUR from Skyworks Solutions is a 6-channel reinforced digital isolator with bidirectional signal isolation across an integrated semiconductor barrier, supporting up to 150 Mbps data rate, 10 ns typical propagation delay, and 6000 VRMS isolation rating. It operates from 2.25–5.5 V on both sides and features Schmitt-trigger + CMOS inputs, tri-state outputs with enable, and selectable fail-safe default-high output mode - used in isolated motor control gate drivers and battery management system communication interfaces.
For engineers reviewing the SI86S662EB-AUR datasheet, SI86S662EB-AUR pinout, SI86S662EB-AUR application, or SI86S662EB-AUR equivalent, key selection criteria include its AEC-Q100 qualification, 6-channel configuration with side-A and side-B enable pins (EN1/EN2), reinforced IEC 60747-17 insulation, and compatibility with industrial and automotive isolated power supply monitoring and SPI peripheral isolation.
Technical Context
The SI86S662EB-AUR implements RF-based on/off keying modulation across a monolithic semiconductor isolation barrier, eliminating startup initialization and enabling deterministic timing behavior. Its architecture supports independent undervoltage lockout (UVLO) and reset circuits per side (VDD1/VDD2), with RSTB thresholds at ~1.7 V and UVLO+ at 2.18 V nominal.
It integrates six isolated digital channels with configurable directionality via external EN1/EN2 control, tri-state output capability, and fail-safe logic state selection during unpowered conditions. The device uses HF XMTR/RCVR circuitry per channel and requires only 0.1 µF and 10 µF bypass capacitors per supply rail - no external magnetics or optocoupler biasing needed.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | DC to 150 Mbps - enables high-speed serial links such as isolated SPI clock domains and real-time motor position feedback. |
| Propagation Delay | 10 ns typical - ensures tight timing alignment between controller and isolated peripherals in closed-loop systems. |
| Isolation Rating | 6000 VRMS for 1 minute - meets reinforced insulation requirements for 1000 VAC working voltage systems per UL 1577. |
| Supply Voltage | 2.25–5.5 V per side - allows interoperability with 3.3 V and 5 V logic families without level-shifting components. |
| Operating Temperature | –40 to +125 °C - supports under-hood automotive and industrial ambient environments without derating. |
| CMTI | ≥100 kV/µs - rejects fast transient coupling in high-noise motor drive and inverter applications. |
| Fail-Safe Mode | Default-high output option - maintains safe logic state during VDD1 loss in isolated gate driver enable paths. |
Pinout & Package
SI86S662EB-AUR is packaged in a WB SOIC-16 (wide-body small-outline integrated circuit) with 16-pin layout and creepage/clearance optimized for 6000 VRMS reinforced isolation. Pin 1 is marked with a dot; pin numbering follows standard SOIC convention (counterclockwise from top-left corner).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Side A power supply | Provides 2.25–5.5 V bias for input-side logic and transmitter circuits; requires local 0.1 µF + 10 µF decoupling. |
| GND1 | Side A ground | Reference return for Side A signals; must be separated from GND2 by ≥8 mm creepage in PCB layout. |
| A1–A6 | Side A digital I/O | Unidirectional or bidirectional isolated inputs/outputs; compatible with CMOS/Schmitt-trigger logic levels. |
| EN1 | Side A output enable | Active-high control: drives all Side A outputs into high-impedance when low - used for bus arbitration or power sequencing. |
| VDD2 | Side B power supply | Independent 2.25–5.5 V supply for output-side logic and receiver circuits; galvanically isolated from VDD1. |
| GND2 | Side B ground | Reference return for Side B signals; forms isolation barrier with GND1; must not share copper pour. |
| B1–B6 | Side B digital I/O | Galvanically isolated mirror of A1–A6; supports synchronous or asynchronous signal transfer across barrier. |
| EN2 | Side B output enable | Active-high control: places all Side B outputs in high-Z state - enables multi-master isolated bus configurations. |
Key Features
| Feature | Design Value |
|---|---|
| RF-based isolation architecture | Eliminates LED aging and temperature drift issues of optocouplers; enables stable 150 Mbps operation over full temperature range. |
| Reinforced IEC 60747-17 rating | Validated for functional safety-critical subsystems including ISO 26262 ASIL-B compliant battery management and traction inverter control. |
| Tri-state outputs with EN1/EN2 | Allows dynamic bus contention management in multi-node isolated SPI or CAN FD transceiver interfaces without external switches. |
| Selectable fail-safe output | Default-high configuration ensures gate driver disable state during primary-side power loss - prevents unintended FET turn-on. |
| AEC-Q100 Grade 0 qualification | Qualified for automotive applications up to +125 °C junction temperature, including onboard chargers and hybrid electric vehicle inverters. |
| High CMTI immunity (≥100 kV/µs) | Rejects common-mode noise from fast-switching SiC/GaN power stages, maintaining signal integrity in high-dV/dt environments. |
Applications
| Motor Control Gate Driver Isolation | Automotive Battery Management System (BMS) |
|---|---|
|
Use Scenario: Isolating PWM signals and fault feedback between MCU and high-voltage IGBT/SiC gate drivers in EV traction inverters. IC Role / Device Role / Timing Role: Six-channel digital isolator providing independent, low-jitter, fail-safe isolation for three-phase upper/lower gate enable and DESAT feedback paths. Use Value: Enables precise 10 ns timing alignment between phase-leg drivers while maintaining 6000 VRMS reinforcement for ASIL-D functional safety compliance. |
Use Scenario: Isolating cell voltage measurement data and balancing command signals between high-voltage battery stack and low-voltage MCU in 800 V BEV packs. IC Role / Device Role / Timing Role: Bidirectional isolator transferring ADC conversion results and balancing enable commands across 400–900 V potential difference. Use Value: Supports 150 Mbps burst-mode telemetry transfer with <3.5 ns pulse width distortion, reducing BMS sampling latency by >40% vs. legacy optocouplers. |
| Industrial Isolated Switch-Mode Power Supply | Isolated SPI Interface for Isolated ADC/DAC |
|
Use Scenario: Providing feedback path for secondary-side voltage/current sensing and primary-side PWM control in 3 kW telecom rectifiers. IC Role / Device Role / Timing Role: Dual-supply isolator with independent EN1/EN2 enabling synchronized shutdown of control loop during overvoltage events. Use Value: Delivers 6000 VRMS isolation with 2.25–5.5 V flexible supply range, eliminating need for auxiliary bias windings or LDOs on isolated side. |
Use Scenario: Isolating SPI clock, MOSI, MISO, and chip select lines between microcontroller and isolated precision ADC (e.g., AD7403) in motor current sensing. IC Role / Device Role / Timing Role: Six-channel isolator configured as four data lines plus two control lines (CS, CLK), preserving full-duplex timing integrity. Use Value: Maintains 150 Mbps data throughput with <10 ns skew between channels, enabling 1 MSPS simultaneous sampling across multiple isolated sensors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM6601ARIZ-RL | 6-channel, 50 Mbps max, integrated isolated DC-DC converter (3.3 V out), no fail-safe output selection. | Suitable where isolated power is required but lower speed suffices; lacks default-high option for safety-critical enable paths. | Choose ADUM6601ARIZ-RL when board space is constrained and isolated 3.3 V supply is needed - SI86S662EB-AUR preferred for 150 Mbps and fail-safe control. |
| ISO6760QDWR | 6-channel, 50 Mbps, 5000 VRMS, no AEC-Q100 qualification, no sleep mode, different pinout (SOIC-16 NB). | Targeted at industrial automation only; not qualified for automotive under-hood use or reinforced medical standards. | Choose ISO6760QDWR for cost-sensitive non-automotive designs; SI86S662EB-AUR required for AEC-Q100, 6000 VRMS, and automotive PPAP support. |
Compared with ADUM6601ARIZ-RL and ISO6760QDWR, SI86S662EB-AUR delivers higher data rate (150 vs. 50 Mbps), certified reinforced 6000 VRMS isolation, AEC-Q100 Grade 0 qualification, and factory-selectable default-high fail-safe mode - making it uniquely suited for automotive traction inverters and high-reliability industrial power supplies.
Availability
SI86S662EB-AUR is available at Aetrix Electronics and suitable for industrial automation systems, automotive battery management systems, and isolated switch-mode power supplies requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI86S662EB-AUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-performance wireless and wired infrastructure.
The Si86S6xx family was designed specifically for high-reliability, high-speed galvanic isolation in automotive and industrial systems - delivering robust RF-based isolation with AEC-Q100 qualification, reinforced safety ratings, and fail-safe configurability.
FAQ
What is the maximum data rate supported by SI86S662EB-AUR?
The SI86S662EB-AUR supports a maximum data rate of 150 Mbps, verified across the full operating temperature range (–40 to +125 °C) and supply voltage range (2.25–5.5 V). This enables high-speed serial protocols such as isolated SPI, digital encoder interfaces, and real-time sensor data streaming without timing bottlenecks. The SI86S662EB-AUR achieves this using RF-based on/off keying modulation, which avoids the bandwidth limitations of traditional optocouplers.
Does SI86S662EB-AUR support fail-safe output configuration?
Yes, SI86S662EB-AUR offers a factory-selectable fail-safe mode that sets the default output state to logic high when the input-side supply (VDD1) is unpowered but the output-side supply (VDD2) remains active. This behavior is confirmed in Table 4 of the datasheet and is critical for safety-critical applications like isolated gate driver enable paths. The SI86S662EB-AUR variant specifically implements the default-high option, ensuring safe shutdown during primary-side power loss.
What isolation rating does SI86S662EB-AUR meet?
SI86S662EB-AUR is rated for 6000 VRMS isolation for 1 minute per UL 1577 and carries reinforced insulation certification per IEC 60747-17. It also complies with CSA 62368-1 and 60601-1, and CQC GB4943.1 - making it suitable for medical, industrial, and automotive applications requiring reinforced barrier integrity. The wide-body SOIC-16 package provides the physical creepage and clearance necessary to sustain this rating.
Is SI86S662EB-AUR qualified for automotive applications?
Yes, SI86S662EB-AUR is AEC-Q100 Grade 0 qualified, meaning it is tested and certified for operation from –40 to +125 °C ambient temperature and validated for use in automotive systems including onboard chargers, battery management systems, and traction inverters. Skyworks provides AIAG-compliant PPAP documentation and IMDS/CAMDS listings specifically for SI86S662EB-AUR and other automotive-grade variants in the Si86S6xx family.
What are the supply voltage requirements for SI86S662EB-AUR?
SI86S662EB-AUR requires two independent supply rails: VDD1 (Side A) and VDD2 (Side B), each operating from 2.25 V to 5.5 V. Both supplies must be decoupled with 0.1 µF ceramic and 10 µF bulk capacitors placed adjacent to their respective pins. The device supports mixed-voltage operation - e.g., 3.3 V on Side A and 5 V on Side B - without level shifters, simplifying interface design with heterogeneous logic families.
SI86S662EB-AUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 6
- Inputs - Side 1/Side 2:
- 4/2
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 2500Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 42ns, 42ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QSOP
SI86S662EB-AUR FAQ
1.How can I place an order for SI86S662EB-AUR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86S662EB-AUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86S662EB-AUR reliable?
The price and inventory of SI86S662EB-AUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86S662EB-AUR is usually 5 days.
3.What payment methods are accepted for SI86S662EB-AUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86S662EB-AUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86S662EB-AUR?
SI86S662EB-AUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86S662EB-AUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86S662EB-AUR?
For technical support, including SI86S662EB-AUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86S662EB-AUR requirements.
6.How does Aetrix verify that SI86S662EB-AUR is sourced from the original manufacturer or authorized distributors?
All SI86S662EB-AUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86S662EB-AUR meets industry standards.
7.What is the process for return or replacement of SI86S662EB-AUR?
All SI86S662EB-AUR units undergo pre-shipment inspection (PSI). If there is an issue with SI86S662EB-AUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86S662EB-AUR part is unused and in its original packaging.
Return procedure for SI86S662EB-AUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86S662EB-AUR Tags
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ISO1212DBQR
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ISO6721BDR
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SI8710AC-B-ISR
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ISO7720FDR
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SI8710CC-B-ISR
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ISO6741FQDWRQ1
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ISO7721DWVR
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ISO7762FDBQR
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ISO7741DWR
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ISO7741FDWR
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