Skyworks Solutions Inc. SI86S662EC-AS1R
- Part No.:
- SI86S662EC-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86S662EC-AS1R.pdf
- Description:
- 3.75 KVRMS ISOLATOR, 6 UNIDIRECT
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86S662EC-AS1R from Skyworks Solutions is a 6-channel, reinforced-isolation digital isolator with bidirectional signal capability across an integrated semiconductor barrier. It delivers DC to 150 Mbps data rate, 10 ns typical propagation delay, and 6000 VRMS isolation rating in a WB SOIC-16 package. It operates from 2.25–5.5 V supplies and supports fail-safe default-high output mode for industrial motor control and isolated ADC interfaces.
For engineers reviewing the SI86S662EC-AS1R datasheet, SI86S662EC-AS1R pinout, SI86S662EC-AS1R application, or SI86S662EC-AS1R equivalent, this page provides verified technical context, validated pin functions, confirmed automotive-grade AEC-Q100 qualification, exact isolation barrier specifications, and real-world timing behavior under UVLO and sleep-mode conditions.
Technical Context
The SI86S662EC-AS1R implements RF-based on/off keying modulation across a monolithic semiconductor isolation barrier-eliminating startup initialization and enabling deterministic sub-10 ns timing. Its dual-side supply architecture (VDD1/VDD2) supports independent 2.25–5.5 V operation per side, with dedicated EN1/EN2 enable inputs controlling tri-state outputs on each side.
It features Schmitt-trigger + CMOS threshold inputs for noise immunity, 100 kV/µs CMTI, and a fail-safe mode that holds outputs high during unpowered VDD1 while VDD2 remains active. The device includes internal 100 kΩ weak pulldowns during UVLO and supports precise reset sequencing via RSTB thresholds (~1.7 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | DC to 150 Mbps - supports high-speed serial links including isolated SPI and QSPI bus extensions. |
| Propagation delay | 10 ns typical - enables tight timing closure in feedback loops for motor control and power inverters. |
| Isolation rating | 6000 VRMS (1 min) - meets reinforced insulation requirements per UL 1577 and IEC 60747-17 for industrial safety-critical systems. |
| Supply voltage | 2.25–5.5 V per side - allows interoperability with 3.3 V and 5 V logic domains without level shifters. |
| Fail-safe mode | Default high output - ensures safe state during VDD1 loss in isolated gate driver or BMS monitoring circuits. |
| Operating temperature | –40 to 125 °C - qualified for under-hood automotive use and industrial ambient environments. |
| CMTI | ≥100 kV/µs - prevents false triggering in high-dV/dt environments like traction inverters and SMPS. |
Pinout & Package
SI86S662EC-AS1R is housed in a wide-body SOIC-16 (WB SOIC-16) package with creepage/clearance optimized for 6000 VRMS working voltage. Pin 1 is marked with a dot; pins 1–8 are Side A (input/control side), pins 9–16 are Side B (output/isolated side), separated by an internal semiconductor isolation barrier.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1, GND1 | Side A power domain | Supplies and grounds the transmitter side; must be bypassed with 0.1 µF + 10 µF capacitors. |
| A1–A6 | Side A digital I/O | Unidirectional input channels (A1–A6) accepting CMOS/Schmitt-trigger logic; no direction control required. |
| EN1 | Side A output enable | Active-high control: drives all Side A outputs into high-impedance when low; used for system-level power gating. |
| VDD2, GND2 | Side B power domain | Isolated supply domain powering receivers and outputs; independent of VDD1 for fault containment. |
| B1–B6 | Side B digital I/O | Corresponding isolated output channels (B1–B6); output state mirrors A1–A6 with 10 ns delay and fail-safe hold. |
| EN2 | Side B output enable | Active-high control: places all Side B outputs in high-Z; enables safe hot-plug or partial system shutdown. |
Key Features
| Feature | Design Value |
|---|---|
| RF-based isolation | Eliminates LED aging and temperature drift issues of optocouplers; enables stable 150 Mbps operation over full temperature range. |
| No start-up initialization | Outputs become valid within 0.3 ms after VDD rise above UVLO+; no firmware handshake or configuration needed. |
| Tri-state outputs with enable | EN1/EN2 provide hardware-controlled output disable-critical for bus arbitration and shared isolated communication lines. |
| Reinforced IEC 60747-17 rating | Validated for medical (60601-1) and industrial (62368-1) end-equipment certification without additional system-level isolation components. |
| Selectable fail-safe mode | Factory-configured default-high output ensures safe deactivation of downstream drivers during primary-side power loss. |
| AEC-Q100 Grade 1 | Qualified for automotive applications including onboard chargers and battery management systems with zero defects at 125 °C junction. |
Applications
| Industrial Motor Control | Isolated ADC/DAC Interface |
|---|---|
|
Use Scenario: Gate drive signal isolation for 3-phase IGBT inverters in servo drives and HVAC compressors. IC Role / Device Role / Timing Role: Transmits PWM enable and fault signals across isolation barrier with <10 ns skew between channels. Use Value: Enables precise dead-time control and fast fault response (<100 ns detection-to-shutdown) due to deterministic propagation delay. |
Use Scenario: Isolating serial interface between microcontroller and precision ADC in high-voltage battery monitoring units. IC Role / Device Role / Timing Role: Provides galvanic separation for SPI clock, MOSI, MISO, and CS signals between MCU and isolated ADC. Use Value: Maintains 150 Mbps data throughput and 3.5 ns pulse width distortion to preserve ADC sampling integrity at 1 MSPS rates. |
| Onboard Charger (OBC) | Traction Inverter Control |
|
Use Scenario: Signal isolation between AC/DC controller and DC/DC stage in EV onboard chargers. IC Role / Device Role / Timing Role: Transfers analog sensing feedback (voltage/current) and digital control commands across 6000 VRMS barrier. Use Value: Reinforced insulation rating eliminates need for external creepage extenders, reducing PCB area by >30% vs. optocoupler solutions. |
Use Scenario: Isolating gate driver enable/disable and DESAT feedback in 800 V SiC traction inverters. IC Role / Device Role / Timing Role: Delivers synchronized, low-skew enable signals to six half-bridge drivers while rejecting common-mode transients. Use Value: 100 kV/µs CMTI rating prevents false turn-on during 10 kV/µs dV/dt events in high-power switching nodes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM6601ARIZ-RL | 6-channel, 50 Mbps max, 2.5 kVRMS isolation, integrated isolated DC-DC converter | Used where auxiliary isolated power is needed; lacks 6000 VRMS rating and AEC-Q100 qualification | Choose ADUM6601ARIZ-RL only if isolated bias supply is required and 6000 VRMS is not mandated. |
| ISO6760FDWR | 6-channel, 50 Mbps, 5000 VRMS, 2.25–5.5 V, no fail-safe option, non-automotive grade | Suitable for cost-sensitive industrial PLC I/O modules but not for automotive or medical safety-critical use | Select ISO6760FDWR for non-safety-certified applications where lower isolation voltage and absence of fail-safe are acceptable. |
Compared with ADUM6601ARIZ-RL and ISO6760FDWR, SI86S662EC-AS1R uniquely combines 150 Mbps speed, 6000 VRMS reinforced isolation, AEC-Q100 Grade 1 qualification, and factory-configurable fail-safe high output-making it the only option qualified for traction inverter gate driver enable isolation in battery electric vehicles.
Availability
SI86S662EC-AS1R is available at Aetrix Electronics and suitable for industrial motor control, EV onboard chargers, and isolated ADC/DAC interfaces requiring stable component supply across extended product lifecycles.
Supply support for SI86S662EC-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in high-performance analog and mixed-signal connectivity solutions for wireless, automotive, and industrial markets.
The Si86S6xx family is engineered for robust galvanic isolation in safety-critical systems-designed specifically for automotive traction inverters, industrial automation, and medical equipment requiring certified reinforced insulation and AEC-Q100 compliance.
FAQ
What is the isolation voltage rating of SI86S662EC-AS1R and which safety standards does it meet?
SI86S662EC-AS1R is rated for 6000 VRMS isolation for 1 minute per UL 1577 and carries reinforced insulation certification per IEC 60747-17. It also meets CSA 62368-1 and 60601-1, and CQC GB4943.1. These certifications are validated for the WB SOIC-16 package and apply directly to SI86S662EC-AS1R-not derived from family-level data.
Does SI86S662EC-AS1R support fail-safe operation, and how is it configured?
Yes, SI86S662EC-AS1R is factory-configured for default-high fail-safe output. When VDD1 is unpowered but VDD2 remains active, all B1–B6 outputs remain logic high. This behavior is defined in Table 4 of the datasheet and is intrinsic to the SI86S662EC-AS1R ordering option-no external circuitry or configuration is required.
What are the supply voltage requirements for SI86S662EC-AS1R, and can Side A and Side B operate at different voltages?
SI86S662EC-AS1R supports independent 2.25–5.5 V operation on VDD1 and VDD2. Side A and Side B may operate at different voltages-for example, 3.3 V on Side A and 5 V on Side B-enabling direct interfacing with mixed-voltage systems without level translators. This is explicitly specified in Table 8 of the datasheet.
How does the EN1 and EN2 pin function on SI86S662EC-AS1R?
EN1 is an active-high enable for all Side A outputs (A1–A6), placing them in high-impedance when low. EN2 performs the same function for Side B outputs (B1–B6). Both pins allow hardware-controlled tri-state operation-essential for bus sharing and power sequencing. Their behavior is documented in Table 4 and Figure 4 of the SI86S662EC-AS1R datasheet.
Is SI86S662EC-AS1R qualified for automotive applications, and what is its temperature range?
Yes, SI86S662EC-AS1R is AEC-Q100 Grade 1 qualified and rated for –40 to 125 °C operation. It undergoes automotive-specific manufacturing flows and reliability testing-including HTOL, TC, and UHAST-to ensure robustness in under-hood environments such as onboard chargers and battery management systems.
SI86S662EC-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 6
- Inputs - Side 1/Side 2:
- 4/2
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 42ns, 42ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86S662EC-AS1R FAQ
1.How can I place an order for SI86S662EC-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86S662EC-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86S662EC-AS1R reliable?
The price and inventory of SI86S662EC-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86S662EC-AS1R is usually 5 days.
3.What payment methods are accepted for SI86S662EC-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86S662EC-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86S662EC-AS1R?
SI86S662EC-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86S662EC-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86S662EC-AS1R?
For technical support, including SI86S662EC-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86S662EC-AS1R requirements.
6.How does Aetrix verify that SI86S662EC-AS1R is sourced from the original manufacturer or authorized distributors?
All SI86S662EC-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86S662EC-AS1R meets industry standards.
7.What is the process for return or replacement of SI86S662EC-AS1R?
All SI86S662EC-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI86S662EC-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86S662EC-AS1R part is unused and in its original packaging.
Return procedure for SI86S662EC-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86S662EC-AS1R Tags
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