Skyworks Solutions Inc. SI86S663EB-AUR
- Part No.:
- SI86S663EB-AUR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
SI86S663EB-AUR.pdf
- Description:
- 2.5 KVRMS ISOLATOR, 6 UNIDIRECTI
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86S663EB-AUR from Skyworks Solutions is a 6-channel reinforced digital isolator with 6000 VRMS isolation, 150 Mbps data rate, and AEC-Q100 qualification for automotive systems. It features dual supply operation (2.25–5.5 V), Schmitt-trigger + CMOS inputs, tri-state outputs with enable, and selectable fail-safe output (default low) for isolated motor control, battery management, and traction inverters.
For engineers reviewing the SI86S663EB-AUR datasheet, SI86S663EB-AUR pinout, SI86S663EB-AUR application, or SI86S663EB-AUR equivalent, key selection criteria include reinforced IEC 60747-17 rating, 10 ns typical propagation delay, 3.5 ns pulse width distortion, transient immunity ≥100 kV/µs, and WB SOIC-16 package compatibility with 8 mm creepage/clearance.
Technical Context
The SI86S663EB-AUR implements RF-based on/off keying across a semiconductor isolation barrier-eliminating startup initialization and providing superior noise immunity versus pulse-based schemes. Its architecture supports independent UVLO and reset monitoring per side (VDD1/VDD2), with RSTB thresholds at ~1.7 V and 100 kΩ weak pulldown during unpowered states.
It delivers bidirectional channel operation with six isolated I/O pairs (A1–A6/B1–B6), active-high EN1/EN2 enables per side, and failsafe default-low output behavior confirmed in Table 4 of the datasheet. No sleep mode (SMb) or direction control (DIR) pins are present-distinguishing it from Si86SMx or Si86SQx variants.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | DC to 150 Mbps - supports high-speed SPI, CAN FD, and real-time control loops without timing bottlenecks. |
| Isolation Rating | 6000 VRMS for 1 minute - meets reinforced insulation requirements per UL 1577 and IEC 60747-17 for automotive BMS and OBC applications. |
| Propagation Delay | 10 ns typical - enables sub-20 ns round-trip latency in closed-loop motor control feedback paths. |
| Pulse Width Distortion | 3.5 ns typical - preserves signal integrity in clock distribution and PWM edge alignment across isolation barrier. |
| Supply Voltage | 2.25–5.5 V per side - interoperable with 3.3 V microcontrollers and 5 V analog front-ends without level shifters. |
| Transient Immunity | ≥100 kV/µs - withstands fast-rising common-mode transients in high-power inverters and industrial drives. |
| Operating Temp | –40 to +125 °C - qualified for under-hood automotive environments and industrial ambient conditions. |
Pinout & Package
SI86S663EB-AUR uses a wide-body SOIC-16 (WB SOIC-16) package with 8.0 mm creepage and clearance, supporting 6000 VRMS reinforced isolation. Pin layout follows Figure 4 (Si86S66x) in the datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1, GND1 | Side A power domain | Supplies and grounds all A-side I/Os (A1–A6); requires 0.1 µF + 10 µF bypass capacitors. |
| A1–A6 | Side A digital I/O | Unidirectional or bidirectional isolated channels; CMOS/Schmitt-trigger compatible with 2.25–5.5 V logic. |
| EN1 | Side A output enable | Active-high control: drives all A-side outputs into high-impedance when low. |
| VDD2, GND2 | Side B power domain | Independent supply domain for B-side I/Os (B1–B6); galvanically isolated from Side A. |
| B1–B6 | Side B digital I/O | Corresponding isolated outputs/inputs mirroring A1–A6; fail-safe defaults to low when VDD1 unpowered. |
| EN2 | Side B output enable | Active-high control: places all B-side outputs in high-impedance state when low. |
Key Features
| Feature | Design Value |
|---|---|
| No startup initialization | RF modulation architecture eliminates boot-up delay-output transitions begin immediately after VDD exceeds UVLO+ (2.18 V typical). |
| Reinforced IEC 60747-17 rating | Validated for functional safety in ASIL-B/C systems; supports end-equipment certification to IEC 62368-1 and IEC 60601-1. |
| Selectable fail-safe mode | SI86S663EB-AUR is factory-configured for default-low output during VDD1 loss-prevents unintended gate drive activation in motor control. |
| High EMI immunity | 100 kV/µs CMTI rating ensures reliable operation near IGBTs, SiC MOSFETs, and switching power supplies. |
| Tri-state outputs with enable | EN1/EN2 allow dynamic bus sharing and hot-swap capability without external logic or pull-ups. |
Applications
| Motor Control Feedback Isolation | Battery Management System (BMS) Communication |
|---|---|
Use Scenario: Isolating encoder signals, current sense ADC outputs, and PWM gate drive commands between MCU and inverter stage in EV traction inverters. IC Role / Device Role / Timing Role: Six-channel digital isolator providing timing-critical, low-latency signal transfer across 6000 VRMS barrier with <10 ns propagation delay. Use Value: Enables safe, high-fidelity current/voltage sampling and gate drive timing while meeting ASIL-D functional safety decomposition requirements. | Use Scenario: Isolating SPI communication between primary controller and cell monitoring ICs in multi-module EV battery packs. IC Role / Device Role / Timing Role: 6-channel isolator handling bidirectional SPI clock, MOSI/MISO, chip select, and fault reporting lines at up to 150 Mbps. Use Value: Maintains deterministic SPI timing across isolation barrier, preventing data corruption during high dv/dt transients in high-voltage battery stacks. |
| Onboard Charger (OBC) Control | Traction Inverter Gate Drive Isolation |
Use Scenario: Isolating digital control signals between AC/DC PFC controller and DC/DC LLC controller in 11 kW automotive OBCs. IC Role / Device Role / Timing Role: Provides six independent isolation paths for voltage reference, error amplifier outputs, enable signals, and status flags. Use Value: Eliminates ground loop noise and enables independent thermal management of control and power stages while sustaining 125 °C junction temperature. | Use Scenario: Isolating high-side and low-side gate drive signals for SiC MOSFET half-bridges in 800 V traction inverters. IC Role / Device Role / Timing Role: Delivers matched propagation delay (<10 ns) and ultra-low pulse width distortion (3.5 ns) to prevent shoot-through in high-frequency switching. Use Value: Supports >100 kHz switching frequencies with precise dead-time control-critical for efficiency and thermal performance in SiC-based inverters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM6630ARIZ-RL | 6-channel, 6000 VRMS, but uses iCoupler magnetic isolation; higher quiescent current (3.5 mA/channel vs. 2.29 mA typical for SI86S663EB-AUR). | Less suitable for AEC-Q100-compliant automotive designs due to lack of automotive-grade qualification and lower CMTI (75 kV/µs). | Prefer SI86S663EB-AUR where automotive qualification, lower power, and higher CMTI are required. |
| ISO6760FDWR | 6-channel, 5000 VRMS (not 6000 VRMS), 50 Mbps max data rate, and no AEC-Q100 qualification. | Limited to industrial automation-not approved for automotive traction or charging systems requiring reinforced 6000 VRMS. | Choose SI86S663EB-AUR for 6000 VRMS compliance, 150 Mbps speed, and automotive qualification. |
Compared with ADUM6630ARIZ-RL and ISO6760FDWR, SI86S663EB-AUR uniquely combines AEC-Q100 qualification, 6000 VRMS reinforced isolation, 150 Mbps bandwidth, and 10 ns propagation delay-making it the only option qualified for safety-critical automotive traction inverter and OBC control loops.
Availability
SI86S663EB-AUR is available at Aetrix Electronics and suitable for automotive onboard chargers, battery management systems, and traction inverters requiring stable component supply with long-term lifecycle support and traceable sourcing.
Supply support for SI86S663EB-AUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si86S6xx family is engineered for high-reliability automotive and industrial isolation-delivering reinforced safety certification, high-speed data integrity, and robust operation in harsh electromagnetic environments.
FAQ
What is the isolation rating and safety certification status of SI86S663EB-AUR?
SI86S663EB-AUR provides 6000 VRMS isolation for 1 minute per UL 1577 and is certified to IEC 60747-17 (reinforced insulation). It holds pending CSA 62368-1 and VDE 60747-17 approvals and is AEC-Q100 qualified for automotive use. The device meets reinforced insulation requirements for medical (IEC 60601-1) and industrial (IEC 62368-1) end equipment.
Does SI86S663EB-AUR support fail-safe operation, and how is it configured?
Yes, SI86S663EB-AUR is factory-configured for default-low fail-safe output during VDD1 undervoltage or loss. When Side A supply falls below UVLO– (1.98 V min), outputs B1–B6 are pulled low via internal circuitry-preventing unintended activation in motor gate drivers or BMS switches. This behavior is confirmed in Table 4 of the datasheet.
What are the supply voltage requirements and bypass capacitor recommendations for SI86S663EB-AUR?
SI86S663EB-AUR operates from 2.25 V to 5.5 V on both VDD1 and VDD2 sides. Each supply requires a 0.1 µF ceramic capacitor placed adjacent to the pin and a 10 µF bulk capacitor nearby. These values are mandatory per Section 3.2.1 of the datasheet to ensure stable operation and noise immunity.
How does the propagation delay and pulse width distortion of SI86S663EB-AUR impact timing-critical applications?
With 10 ns typical propagation delay and 3.5 ns typical pulse width distortion, SI86S663EB-AUR maintains tight timing margins in high-speed motor control and gate drive circuits. These specs enable accurate PWM edge alignment and prevent shoot-through in SiC half-bridges-directly supporting >100 kHz switching frequencies in traction inverters.
Is SI86S663EB-AUR pin-compatible with other devices in the Si86S6xx family?
SI86S663EB-AUR shares the same WB SOIC-16 pinout as SI86S660, SI86S661, SI86S662, and SI86S663 variants (Figure 4). All use identical A1–A6/B1–B6 I/O mapping and EN1/EN2 enable pins. Differences are limited to internal fail-safe configuration (default low) and ordering suffix-no PCB redesign is needed when substituting within the S66x group.
SI86S663EB-AUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 6
- Inputs - Side 1/Side 2:
- 3/3
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 2500Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 42ns, 42ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QSOP
SI86S663EB-AUR FAQ
1.How can I place an order for SI86S663EB-AUR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86S663EB-AUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86S663EB-AUR reliable?
The price and inventory of SI86S663EB-AUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86S663EB-AUR is usually 5 days.
3.What payment methods are accepted for SI86S663EB-AUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86S663EB-AUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86S663EB-AUR?
SI86S663EB-AUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86S663EB-AUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86S663EB-AUR?
For technical support, including SI86S663EB-AUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86S663EB-AUR requirements.
6.How does Aetrix verify that SI86S663EB-AUR is sourced from the original manufacturer or authorized distributors?
All SI86S663EB-AUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86S663EB-AUR meets industry standards.
7.What is the process for return or replacement of SI86S663EB-AUR?
All SI86S663EB-AUR units undergo pre-shipment inspection (PSI). If there is an issue with SI86S663EB-AUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86S663EB-AUR part is unused and in its original packaging.
Return procedure for SI86S663EB-AUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86S663EB-AUR Tags
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ISO1212DBQR
Texas Instruments

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ISO6721BDR
Texas Instruments

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SI8710AC-B-ISR
Skyworks Solutions Inc.

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ISO7720FDR
Texas Instruments

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ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

-
SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

-
ISO7721DWVR
Texas Instruments
-
ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
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