Skyworks Solutions Inc. SI86SL40EC-AS1R
- Part No.:
- SI86SL40EC-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86SL40EC-AS1R.pdf
- Description:
- 3.75 KVRMS LOW POWER ISOLATOR, 4
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86SL40EC-AS1R from Skyworks Solutions is a 4-channel, low-power digital isolator with reinforced 6000 VRMS isolation, 150 Mbps data rate, and AEC-Q100 qualification for automotive systems. It features Schmitt-trigger CMOS inputs, tri-state outputs with enable, selectable fail-safe (default-high) mode, and operates across –40 to 125 °C with 2.25–5.5 V dual supplies. It is used in battery management systems and onboard chargers where high noise immunity and safety-certified signal isolation are critical.
For engineers reviewing the SI86SL40EC-AS1R datasheet, SI86SL40EC-AS1R pinout, SI86SL40EC-AS1R application, or SI86SL40EC-AS1R equivalent, key selection criteria include its 6000 VRMS reinforced insulation per UL 1577 and VDE 60747-17, 10 ns typical propagation delay, 3.5 ns pulse width distortion, 100 kV/µs CMTI, and SOIC-16 wide-body package compatibility with automotive PPAP requirements.
Technical Context
The SI86SL40EC-AS1R implements RF-based on/off keying across a semiconductor isolation barrier-eliminating startup initialization and enabling robust noise immunity without optical degradation. Its architecture supports bidirectional channel operation with independent side-A and side-B supply domains, each featuring undervoltage lockout (UVLO) and reset circuitry referenced to 2.18 V (rising) and 2.05 V (falling).
It integrates sleep-mode control via SMb pin (active-low), reducing quiescent current to 750 µA per side while retaining one active channel for wake-up detection. The device uses HF XMTR/RCVR functional blocks per channel and supports fail-safe output states during unpowered conditions on either side, configurable at order time as default-high ('H' suffix in part number).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | DC to 150 Mbps - supports high-speed serial links including isolated SPI and QSPI interfaces without timing bottlenecks. |
| Isolation rating | 6000 VRMS (1 min) - meets reinforced insulation requirements per UL 1577 and VDE 60747-17 for automotive and industrial safety-critical systems. |
| Propagation delay | 10 ns (typical) - enables precise timing alignment in motor control gate drivers and ADC sampling clocks. |
| Pulse width distortion | 3.5 ns (typical) - ensures minimal duty-cycle error in PWM-isolated feedback loops. |
| CMTI | ≥100 kV/µs - maintains signal integrity in high-dV/dt environments such as traction inverters and SiC/GaN power stages. |
| Supply voltage | 2.25–5.5 V per side - allows direct interfacing with 3.3 V microcontrollers and 5 V analog subsystems without level-shifting. |
| Operating temperature | –40 to 125 °C - qualified for under-hood automotive applications including battery electric vehicle (BEV) powertrain modules. |
Pinout & Package
SI86SL40EC-AS1R is housed in a WB SOIC-16 (wide-body SOIC-16) package with creepage/clearance optimized for 6000 VRMS working voltage. Pin 1 is marked with a dot; the isolation barrier separates Side A (pins 1–8) and Side B (pins 9–16).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Side A power supply | Supplies 2.25–5.5 V to input-side logic and transmitters; requires 0.1 µF + 10 µF bypass capacitors. |
| GND1 | Side A ground | Reference for Side A I/O and supply; must be separated from GND2 by ≥8 mm creepage in PCB layout. |
| A1–A4 | Side A digital I/O | Four isolated input/output channels on Side A; support Schmitt-trigger thresholds for noise rejection. |
| SMb | Sleep mode control | Active-low pin enabling ultra-low-power state (750 µA/side); retains wake-up capability via dedicated HF RCVR path. |
| GND2 | Side B ground | Reference for Side B logic; galvanically isolated from GND1; defines secondary-side return path. |
| B1–B4 | Side B digital I/O | Four isolated output/input channels on Side B; electrically independent of Side A with separate VDD2 supply. |
| VDD2 | Side B power supply | Supplies 2.25–5.5 V to output-side logic and receivers; decoupling required adjacent to pins 15–16. |
Key Features
| Feature | Design Value |
|---|---|
| No-startup initialization | RF modulation architecture eliminates boot-time delays or configuration sequences-output follows input immediately after UVLO exit. |
| Selectable fail-safe mode | Ordering option 'EC' specifies default-high output during VDD1/VDD2 brownout-prevents unintended actuation in BMS fault conditions. |
| Tri-state outputs with EN | EN1/EN2 pins (not present on SI86SL40EC-AS1R; replaced by SMb) are superseded by SMb-controlled tristate-enables bus sharing in multi-device isolated networks. |
| High electromagnetic immunity | 100 kV/µs common-mode transient immunity ensures reliable operation near high-power switching nodes in inverters and OBCs. |
| AEC-Q100 Grade 1 | Qualified for automotive use up to 125 °C ambient; includes AIAG-compliant PPAP documentation and IMDS/CAMDS material declarations. |
Applications
| Battery Management System (BMS) | Onboard Charger (OBC) |
|---|---|
Use Scenario: Isolating cell voltage monitoring ADC signals and pack contactor control commands between high-voltage battery stack and low-voltage MCU domain. IC Role / Device Role / Timing Role: SI86SL40EC-AS1R provides four independent, safety-certified signal paths: two for isolated analog front-end data acquisition and two for isolated digital control outputs. Use Value: 6000 VRMS reinforced isolation prevents high-voltage transients from damaging MCU peripherals; 10 ns propagation delay preserves sampling synchronization across multiple cells. | Use Scenario: Galvanic separation of primary-side PWM controller signals and secondary-side rectifier gate drive feedback in bidirectional AC/DC converters. IC Role / Device Role / Timing Role: SI86SL40EC-AS1R delivers isolated gate drive enable/disable and current-sense amplifier output signals across the isolation barrier in OBC power stage control loop. Use Value: 150 Mbps data rate supports fast closed-loop response; CMTI ≥100 kV/µs prevents false triggering during SiC MOSFET switching transitions. |
| Traction Inverter Control | Charging Station Communication Interface |
Use Scenario: Isolating IGBT/SiC gate driver inputs and fault reporting signals between inverter control board and high-power gate driver stage in EV powertrain. IC Role / Device Role / Timing Role: SI86SL40EC-AS1R carries isolated PWM inputs, DESAT feedback, and overtemperature alerts across the barrier with deterministic latency. Use Value: Pulse width distortion ≤3.5 ns ensures accurate dead-time implementation; –40 to 125 °C operation sustains reliability in under-hood thermal environments. | Use Scenario: Isolating CAN FD communication lines and status LED control signals between charging station's main controller and high-voltage DC output module. IC Role / Device Role / Timing Role: SI86SL40EC-AS1R isolates CAN TX/RX differential pairs and two GPIOs for HV interlock and ready-status indication. Use Value: AEC-Q100 qualification validates long-term stability in outdoor deployment; SOIC-16 WB package meets IPC-2221 creepage requirements for 1000 V DC systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM4402ARWZ | 4-channel, 100 Mbps, 5000 VRMS, 2.7–5.5 V, non-AEC-Q100, SOIC-16 narrow body | Lacks automotive qualification and 6000 VRMS rating; lower CMTI (75 kV/µs) | Use where cost sensitivity outweighs automotive compliance and higher isolation voltage. |
| ISO7741FDWR | 4-channel, 100 Mbps, 5000 VRMS, 2.25–5.5 V, AEC-Q100 Grade 1, SOIC-16 wide body | Lower data rate and isolation rating than SI86SL40EC-AS1R; identical package footprint | Acceptable for non-safety-critical 100 Mbps links where full 150 Mbps headroom is unnecessary. |
Compared with ADUM4402ARWZ and ISO7741FDWR, SI86SL40EC-AS1R delivers higher isolation voltage (6000 vs. 5000 VRMS), faster data throughput (150 vs. 100 Mbps), and superior noise immunity (100 vs. 75 kV/µs CMTI), making it optimal for next-generation BEV power electronics requiring extended lifetime and functional safety margins.
Availability
SI86SL40EC-AS1R is available at Aetrix Electronics and suitable for battery management systems, onboard chargers, and traction inverter control requiring stable component supply across automotive production lifecycles.
Supply support for SI86SL40EC-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for wireless, automotive, and industrial markets.
The Si86Sxx family-including SI86SL40EC-AS1R-is engineered for high-reliability signal isolation in safety-critical automotive and industrial power systems, emphasizing reinforced insulation, AEC-Q100 compliance, and RF-based noise resilience.
FAQ
What is the isolation voltage rating of SI86SL40EC-AS1R and which safety standards does it meet?
SI86SL40EC-AS1R provides 6000 VRMS reinforced isolation for 1 minute per UL 1577 and complies with VDE 60747-17, CSA 62368-1/60601-1, and CQC GB4943.1. This rating is validated for the WB SOIC-16 package and supports end-equipment certification in automotive battery systems and medical power supplies.
Does SI86SL40EC-AS1R require external configuration or startup initialization?
No. SI86SL40EC-AS1R uses RF on/off keying across a semiconductor barrier and begins transmitting valid data immediately after both VDD1 and VDD2 exceed their UVLO+ thresholds (~2.18 V). There is no firmware, register setup, or calibration needed-making it truly plug-and-play for isolated signal paths.
What is the function of the SMb pin on SI86SL40EC-AS1R?
The SMb pin on SI86SL40EC-AS1R is an active-low sleep mode control that reduces total quiescent current to 750 µA per side. When pulled low, it disables all transmitter/receiver circuits except one dedicated HF RCVR path that monitors SMb state-allowing instant wake-up when SMb is released or driven high.
How does SI86SL40EC-AS1R handle power loss on one side of the isolation barrier?
SI86SL40EC-AS1R implements fail-safe operation per ordering option 'EC', meaning outputs default to logic high when either VDD1 or VDD2 falls below UVLO–. This behavior is hardwired and ensures safe shutdown states-for example, holding BMS contactor drivers high to maintain open-circuit protection during MCU brownout.
Is SI86SL40EC-AS1R compatible with standard SOIC-16 footprints?
Yes-SI86SL40EC-AS1R uses the WB (wide-body) SOIC-16 package with 10.3 mm body width and 1.27 mm pitch, matching JEDEC MS-013AC. It is not pin-compatible with narrow-body SOIC-16 (3.9 mm width), but shares land pattern dimensions with other Skyworks Si86Sxx wide-body variants like SI8660BD-B-IS1R.
SI86SL40EC-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 4/0
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 18ns, 18ns
- Pulse Width Distortion (Max):
- 7ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86SL40EC-AS1R FAQ
1.How can I place an order for SI86SL40EC-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86SL40EC-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86SL40EC-AS1R reliable?
The price and inventory of SI86SL40EC-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86SL40EC-AS1R is usually 5 days.
3.What payment methods are accepted for SI86SL40EC-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86SL40EC-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86SL40EC-AS1R?
SI86SL40EC-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86SL40EC-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86SL40EC-AS1R?
For technical support, including SI86SL40EC-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86SL40EC-AS1R requirements.
6.How does Aetrix verify that SI86SL40EC-AS1R is sourced from the original manufacturer or authorized distributors?
All SI86SL40EC-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86SL40EC-AS1R meets industry standards.
7.What is the process for return or replacement of SI86SL40EC-AS1R?
All SI86SL40EC-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI86SL40EC-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86SL40EC-AS1R part is unused and in its original packaging.
Return procedure for SI86SL40EC-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86SL40EC-AS1R Tags
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ISO1212DBQR
Texas Instruments

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ISO6721BDR
Texas Instruments

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SI8710AC-B-ISR
Skyworks Solutions Inc.

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ISO7720FDR
Texas Instruments

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ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

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SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

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ISO7721DWVR
Texas Instruments
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ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
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