Skyworks Solutions Inc. SI86SL40EE-AS2
- Part No.:
- SI86SL40EE-AS2
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
SI86SL40EE-AS2.pdf
- Description:
- 6.0 KVRMS LOW POWER ISOLATOR, 4
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86SL40EE-AS2 from Skyworks Solutions is a 4-channel, low-power digital isolator with reinforced 6000 VRMS isolation, 150 Mbps data rate, and AEC-Q100 qualification for automotive systems. It features Schmitt-trigger inputs, tri-state outputs with enable, selectable fail-safe default (high/low), and operates across –40 to 125 °C in WB SOIC-16 package. It is used in battery management systems and isolated ADC interfaces where high noise immunity and safety-certified signal transfer are required.
For engineers reviewing the SI86SL40EE-AS2 datasheet, SI86SL40EE-AS2 pinout, SI86SL40EE-AS2 application, or SI86SL40EE-AS2 equivalent, key selection criteria include its 6000 VRMS reinforced insulation per UL 1577 and VDE 60747-17, 10 ns typical propagation delay, 3.5 ns pulse width distortion, 100 kV/µs CMTI, and sleep-mode support via SMb pin for power-sensitive automotive subsystems.
Technical Context
The SI86SL40EE-AS2 implements RF-based on/off keying across a semiconductor isolation barrier, eliminating start-up initialization and enabling robust noise immunity without optical degradation. Its architecture supports bidirectional channel operation with independent side-A and side-B undervoltage lockout (UVLO) and reset thresholds (RSTB± ~1.7 V).
It integrates sleep mode control via active-low SMb pin, reducing quiescent current to 750 µA per side while retaining one always-active channel for wake-up detection. The device uses CMOS thresholds and requires only 0.1 µF + 10 µF bypass capacitors per supply rail - no external biasing or timing components needed.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | DC to 150 Mbps - supports high-speed SPI, CAN FD, and real-time control loop signaling without protocol translation. |
| Isolation rating | 6000 VRMS (1 min, UL 1577) - enables use in 1000 VAC+ industrial and traction inverter gate drive circuits. |
| Propagation delay | 10 ns typical - ensures sub-20 ns round-trip latency for time-critical feedback paths in motor control. |
| Pulse width distortion | 3.5 ns typical - preserves duty cycle integrity for PWM and clock forwarding applications. |
| CMTI | ≥100 kV/µs - rejects fast transients from IGBT switching in EV inverters and isolated DC-DC converters. |
| Supply voltage | 2.25–5.5 V per side - allows direct interfacing with 3.3 V microcontrollers and 5 V analog front-ends without level shifters. |
| Operating temperature | –40 to 125 °C - meets under-hood automotive requirements for onboard chargers and battery monitors. |
Pinout & Package
SI86SL40EE-AS2 is housed in a wide-body SOIC-16 (WB SOIC-16) package with 8.0 mm creepage/clearance, supporting 6000 VRMS reinforced insulation. Pinout matches Si86S64x/L4x family (Figure 2, datasheet p.2).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1, GND1 | Side A power supply | Independent 2.25–5.5 V domain for controller-side logic; requires local 0.1 µF + 10 µF decoupling. |
| A1–A4 | Side A digital I/O | Four unidirectional input channels; Schmitt-trigger inputs tolerate slow edges and reject <36 ns glitches. |
| SMb | Sleep mode control | Active-low pin that disables all transmitters except one wake-up channel; pulls device to 750 µA/side quiescent. |
| Isolation Barrier | Die-level separation | Semiconductor-based RF barrier - no LED aging, no optocoupler CTR drift, guaranteed 60-year lifetime per FIT analysis. |
| B1–B4 | Side B digital I/O | Four isolated output channels; tri-state capable via EN2; fail-safe default set at order time (high/low). |
| VDD2, GND2 | Side B power supply | Galvanically isolated 2.25–5.5 V domain for sensor/actuator side; UVLO and RSTB monitoring per side. |
Key Features
| Feature | Design Value |
|---|---|
| Reinforced IEC 60747-17 rating | Validated for functional safety in ASIL-B automotive systems and medical 60601-1 applications. |
| Low-power optimized architecture | 0.25 mA/channel lower quiescent current vs. Si86S6x - reduces thermal load in sealed battery enclosures. |
| Selectably fail-safe output | Factory-configured default state (high/low) during VDD loss - prevents undefined gate driver states in power stages. |
| RF modulation scheme | No start-up delay or handshake required - outputs stabilize within 0.3 ms after VDD rise above 2.18 V. |
| High CMTI immunity | 100 kV/µs minimum - sustains reliable operation adjacent to 1200 V SiC MOSFETs switching at 100 kHz. |
Applications
| Battery Management System (BMS) | Isolated ADC Interface |
|---|---|
|
Use Scenario: Monitoring cell voltages and temperatures in 400–800 V EV battery packs with galvanic separation between MCU and sensing ICs. IC Role / Device Role / Timing Role: Isolates serial data (e.g., LTC6813 daisy-chain) and fault signals across high-voltage domains while preserving 150 Mbps throughput. Use Value: Enables safe, high-resolution SOC estimation using reinforced 6000 VRMS isolation - eliminates risk of ground-loop-induced measurement error. |
Use Scenario: Interfacing isolated sigma-delta ADCs (e.g., AMC1306) to host processors in motor drives and energy meters. IC Role / Device Role / Timing Role: Transfers oversampled bitstreams across isolation barrier with <10 ns jitter - critical for maintaining ENOB in 24-bit conversions. Use Value: Maintains 3.5 ns pulse width distortion to prevent duty-cycle skew in clock-forwarding paths, ensuring accurate digital filter alignment. |
| Onboard Charger (OBC) | Traction Inverter Control |
|
Use Scenario: Isolating communication between AC/DC and DC/DC stages in bi-directional OBCs for Level 2 charging. IC Role / Device Role / Timing Role: Carries CAN FD messages and status flags across 600 VDC intermediate bus with AEC-Q100 compliance. Use Value: Supports 150 Mbps data rate to handle full CAN FD payloads (64 bytes) at 5 Mbps without bottlenecking system diagnostics. |
Use Scenario: Transmitting PWM dead-time control and fault feedback between MCU and isolated gate drivers in 800 V traction inverters. IC Role / Device Role / Timing Role: Delivers <10 ns propagation delay and 100 kV/µs CMTI to ensure precise timing alignment of IGBT/SiC gate signals. Use Value: Prevents shoot-through by guaranteeing sub-20 ns round-trip latency for overcurrent trip signals - critical for ASIL-D functional safety. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM4402BRIZ | 4-channel, 100 Mbps, 5000 VRMS, 15 ns propagation delay, no sleep mode, 2.7–5.5 V supply. | Lacks AEC-Q100 qualification and 6000 VRMS rating - suitable for industrial but not automotive traction systems. | Choose ADUM4402BRIZ when cost sensitivity outweighs need for automotive qualification and highest isolation voltage. |
| ISO7741FDWR | 4-channel, 100 Mbps, 5000 VRMS, 11 ns propagation delay, 2.25–5.5 V, no SMb pin, TI's reinforced isolation. | Does not support sleep mode or selectable fail-safe; certified to VDE 60747-17 but rated only to 5000 VRMS. | Prefer ISO7741FDWR for non-automotive industrial PLCs where 5000 VRMS suffices and TI ecosystem integration is prioritized. |
Compared with ADUM4402BRIZ and ISO7741FDWR, SI86SL40EE-AS2 delivers higher isolation (6000 VRMS), faster timing (10 ns vs. ≥11 ns), automotive qualification, and integrated sleep mode - making it uniquely suited for next-generation EV power electronics requiring ASIL-B compliance and ultra-low standby power.
Availability
SI86SL40EE-AS2 is available at Aetrix Electronics and suitable for battery management systems, onboard chargers, and traction inverter control requiring stable component supply across automotive production lifecycles.
Supply support for SI86SL40EE-AS2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-reliability markets.
The Si86Sxx family was designed specifically for automotive and industrial isolation needs - delivering reinforced safety certification, extended temperature operation, and RF-based reliability superior to optocouplers and capacitive isolators.
FAQ
What is the isolation voltage rating of the SI86SL40EE-AS2 and which standards does it meet?
The SI86SL40EE-AS2 provides 6000 VRMS isolation for 1 minute per UL 1577 and is certified to VDE 60747-17 for reinforced insulation. It also meets CSA 62368-1 and CQC GB4943.1 requirements. These ratings are validated for the WB SOIC-16 package and apply directly to the SI86SL40EE-AS2 - no derating is required for standard PCB layouts meeting creepage/clearance guidelines.
Does the SI86SL40EE-AS2 support fail-safe output configuration, and how is it implemented?
Yes, the SI86SL40EE-AS2 offers factory-selectable fail-safe mode: default high or default low output during input-side power loss. This behavior is hard-coded at manufacture and reflected in the part number suffix (e.g., "EE" denotes one specific fail-safe option). The SI86SL40EE-AS2 maintains this configured state as long as VDD2 remains powered, preventing undefined logic states in safety-critical power stages.
How does the SMb pin function on the SI86SL40EE-AS2, and what power savings does it enable?
The SMb pin on the SI86SL40EE-AS2 is an active-low sleep mode control that reduces total quiescent current to 750 µA per side. When pulled low, it disables all transmitter circuits except one dedicated wake-up channel. The SI86SL40EE-AS2 exits sleep mode within 1 µs when SMb is released high or left open - enabling rapid response in battery-powered automotive subsystems.
What are the key timing specifications of the SI86SL40EE-AS2, and how do they impact real-time control systems?
The SI86SL40EE-AS2 delivers 10 ns typical propagation delay and 3.5 ns typical pulse width distortion. These values ensure minimal signal skew across all four channels - critical for synchronized PWM generation, encoder feedback, and isolated current sensing in motor drives. The SI86SL40EE-AS2 maintains these specs across –40 to 125 °C and 2.25–5.5 V supply range without calibration.
Is the SI86SL40EE-AS2 qualified for automotive applications, and what documentation is available?
Yes, the SI86SL40EE-AS2 is AEC-Q100 qualified for Grade 1 (–40 to 125 °C) operation and supports AIAG-compliant PPAP documentation. Skyworks provides IMDS and CAMDS material declarations, along with full safety certification reports (UL, VDE, CSA) - all applicable to the SI86SL40EE-AS2 as shipped, not just the base family.
SI86SL40EE-AS2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 4/0
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 6000Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 18ns, 18ns
- Pulse Width Distortion (Max):
- 7ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86SL40EE-AS2 FAQ
1.How can I place an order for SI86SL40EE-AS2 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86SL40EE-AS2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86SL40EE-AS2 reliable?
The price and inventory of SI86SL40EE-AS2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86SL40EE-AS2 is usually 5 days.
3.What payment methods are accepted for SI86SL40EE-AS2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86SL40EE-AS2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86SL40EE-AS2?
SI86SL40EE-AS2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86SL40EE-AS2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86SL40EE-AS2?
For technical support, including SI86SL40EE-AS2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86SL40EE-AS2 requirements.
6.How does Aetrix verify that SI86SL40EE-AS2 is sourced from the original manufacturer or authorized distributors?
All SI86SL40EE-AS2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86SL40EE-AS2 meets industry standards.
7.What is the process for return or replacement of SI86SL40EE-AS2?
All SI86SL40EE-AS2 units undergo pre-shipment inspection (PSI). If there is an issue with SI86SL40EE-AS2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86SL40EE-AS2 part is unused and in its original packaging.
Return procedure for SI86SL40EE-AS2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86SL40EE-AS2 Tags
-
ISO1212DBQR
Texas Instruments

-
ISO6721BDR
Texas Instruments

-
SI8710AC-B-ISR
Skyworks Solutions Inc.

-
ISO7720FDR
Texas Instruments

-
ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

-
SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

-
ISO7721DWVR
Texas Instruments
-
ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
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