Skyworks Solutions Inc. SI86SL40HC-IS1R
- Part No.:
- SI86SL40HC-IS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86SL40HC-IS1R.pdf
- Description:
- 3.75 KVRMS LOW POWER ISOLATOR, 4
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86SL40HC-IS1R from Skyworks Solutions is a 4-channel, low-power digital isolator with reinforced 6000 VRMS isolation, 150 Mbps data rate, and AEC-Q100 qualification for automotive systems. It features Schmitt-trigger CMOS inputs, tri-state outputs with enable, selectable fail-safe default (high/low), and operates across –40 to 125 °C in WB SOIC-16 package. It is used in isolated ADC/DAC interfaces and battery management systems where high noise immunity and safety-certified signal integrity are required.
For engineers reviewing the SI86SL40HC-IS1R datasheet, SI86SL40HC-IS1R pinout, SI86SL40HC-IS1R application, or SI86SL40HC-IS1R equivalent, key selection criteria include its 6000 VRMS reinforced insulation per UL 1577 and VDE 60747-17, 10 ns typical propagation delay, 3.5 ns pulse width distortion, sleep-mode support via SMb pin, and compatibility with industrial and automotive isolated communication buses.
Technical Context
The SI86SL40HC-IS1R implements RF-based on/off keying across a semiconductor isolation barrier-eliminating startup initialization and enabling robust noise immunity up to 100 kV/µs. Its architecture supports bidirectional channel operation with side-specific enable (EN1/EN2) and active-low sleep control (SMb), allowing dynamic power gating without compromising CMTI performance.
It delivers precise timing with 10 ns propagation delay and 3.5 ns pulse width distortion while maintaining 2.25–5.5 V dual-supply flexibility on both sides. Fail-safe output state (default high or low) is determined by ordering option and remains stable during undervoltage lockout (UVLO) events triggered below 2.18 V on either VDD1 or VDD2.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | DC to 150 Mbps - supports high-speed SPI, QSPI, and serial bus isolation without protocol translation. |
| Isolation rating | 6000 VRMS - enables reinforced insulation per UL 1577, VDE 60747-17, and CSA 62368-1 for safety-critical automotive and medical applications. |
| Propagation delay | 10 ns (typical) - ensures tight timing alignment between isolated controller and peripheral in real-time motor control loops. |
| Pulse width distortion | 3.5 ns (typical) - preserves duty cycle fidelity for clock forwarding and PWM signal isolation. |
| Supply voltage | 2.25–5.5 V per side - allows interoperability with 3.3 V and 5 V logic domains without level shifters. |
| Operating temperature | –40 to 125 °C - qualified for under-hood automotive use and industrial environments with wide thermal cycling. |
| Transient immunity | ≥100 kV/µs - rejects fast common-mode transients in switching power supplies and traction inverters. |
| Sleep current | 750 µA per side - reduces system standby power when SMb is asserted, critical for always-on BMS monitoring. |
Pinout & Package
SI86SL40HC-IS1R is housed in a wide-body SOIC-16 (WB SOIC-16) package with creepage/clearance compliant for 6000 VRMS working voltage. Pin assignments follow the Si86SL4x family layout: Side A (pins 1–8) and Side B (pins 9–16) are separated by an internal semiconductor isolation barrier.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1, GND1 | Side A power supply | Provides independent 2.25–5.5 V bias for input-side logic; requires local 0.1 µF + 10 µF bypassing. |
| A1–A4 | Side A digital I/O | Four unidirectional or bidirectional channels (configurable per direction control); Schmitt-trigger inputs reject noise. |
| EN1 | Side A output enable | Active-high control for tri-stating all A-side outputs - enables shared-bus arbitration and hot-swap capability. |
| SMb | Sleep mode control | Active-low pin that disables internal transmitters/receivers except one monitoring channel; reduces quiescent current to 750 µA/side. |
| VDD2, GND2 | Side B power supply | Galvanically isolated 2.25–5.5 V bias for output-side logic; decoupling identical to Side A. |
| B1–B4 | Side B digital I/O | Isolated mirror of A1–A4; maintains signal integrity across 6000 VRMS barrier with <10 ns skew. |
| EN2 | Side B output enable | Independent tri-state control for B-side outputs - supports asymmetric enable sequencing in multi-isolator systems. |
Key Features
| Feature | Design Value |
|---|---|
| RF-based isolation | Eliminates LED aging and temperature drift issues of optocouplers; no start-up initialization required. |
| Reinforced insulation | 6000 VRMS withstand per UL 1577 and VDE 60747-17 - certified for functional safety in ASIL-B/C automotive subsystems. |
| Selectable fail-safe mode | Ordering option determines default output state (high or low) during VDD loss - prevents undefined states in BMS fault detection. |
| Low-power optimization | 0.25 mA/channel lower quiescent current vs. Si86S6x - extends battery life in always-on vehicle monitoring circuits. |
| High CMTI | ≥100 kV/µs common-mode transient immunity - maintains data integrity in noisy 1000 V DC bus environments. |
| Schmitt-trigger inputs | 0.15 × VDD hysteresis - rejects sub-36 ns noise glitches without external filtering, reducing BOM count. |
Applications
| Motor Control Feedback Isolation | Isolated ADC Interface |
|---|---|
|
Use Scenario: Isolating encoder signals and gate driver status feedback in 400 V traction inverters. IC Role / Device Role / Timing Role: SI86SL40HC-IS1R provides four independent, low-skew channels to transmit position, speed, and fault signals across the isolation barrier with <10 ns propagation delay. Use Value: Enables real-time closed-loop control with deterministic latency, meeting ISO 26262 ASIL-B timing requirements for torque safety. |
Use Scenario: Connecting SAR ADCs to microcontrollers in isolated sensor front-ends for battery cell voltage monitoring. IC Role / Device Role / Timing Role: SI86SL40HC-IS1R isolates serial data, clock, and chip select lines between ADC and MCU while preserving 150 Mbps throughput. Use Value: Maintains 16-bit resolution integrity by eliminating ground loop noise and enabling simultaneous sampling across multiple cells. |
| Onboard Charger Communication | Traction Inverter Gate Driver Interface |
|
Use Scenario: Isolating CAN FD and analog sensing signals between OBC controller and AC/DC stage in EV charging systems. IC Role / Device Role / Timing Role: SI86SL40HC-IS1R handles bidirectional digital control and isolated analog monitoring signals with fail-safe default-low configuration. Use Value: Ensures safe shutdown during brownout events by forcing low-level gate disable signals to prevent shoot-through faults. |
Use Scenario: Transmitting PWM and DESAT feedback between DSP and SiC gate drivers in 800 V inverter modules. IC Role / Device Role / Timing Role: SI86SL40HC-IS1R delivers <3.5 ns pulse width distortion to preserve dead-time accuracy and isolate DESAT fault signals within 100 ns. Use Value: Prevents false triggering of overcurrent protection and enables reliable short-circuit response in high-dV/dt SiC systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM140D0BRIZ | 4-channel, 150 Mbps, 3750 VRMS isolation, 2.5–5.5 V supply, no sleep mode, 15 ns propagation delay. | Lacks reinforced 6000 VRMS rating and AEC-Q100 qualification - suitable for industrial but not automotive safety-critical use. | Choose ADUM140D0BRIZ only for cost-sensitive non-automotive designs where 3750 VRMS suffices and sleep mode is unnecessary. |
| ISO6741FDWR | 4-channel, 50 Mbps, 5000 VRMS, 1.71–5.5 V, integrated LDO, 11 ns propagation delay, no SMb pin. | Lower data rate limits SPI/QSPI use; lacks sleep control and failsafe selection - better for low-speed sensor isolation. | Prefer ISO6741FDWR when integrating regulated 3.3 V supply for downstream peripherals is needed and 150 Mbps is not required. |
Compared with ADUM140D0BRIZ and ISO6741FDWR, SI86SL40HC-IS1R uniquely combines AEC-Q100 qualification, 6000 VRMS reinforced insulation, 150 Mbps bandwidth, and active-low sleep control - making it the only option qualified for ASIL-B traction inverter communication and BMS real-time monitoring.
Availability
SI86SL40HC-IS1R is available at Aetrix Electronics and suitable for automotive battery management systems, traction inverter control, onboard charger communication, and isolated ADC/DAC interfaces requiring stable component supply across extended temperature and safety certification lifecycles.
Supply support for SI86SL40HC-IS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and isolation technologies for wireless, automotive, and industrial markets.
The Si86SLx family was designed specifically for low-power, high-reliability digital isolation in automotive electrification systems - emphasizing AEC-Q100 compliance, reinforced safety certification, and sleep-mode efficiency for always-on monitoring.
FAQ
What is the isolation voltage rating of SI86SL40HC-IS1R and which safety standards does it meet?
SI86SL40HC-IS1R provides 6000 VRMS reinforced isolation per UL 1577 for 1 minute and complies with VDE 60747-17, CSA 62368-1, and CQC GB4943.1. This rating is validated for the WB SOIC-16 package and enables use in ASIL-B automotive subsystems and medical equipment requiring double insulation.
Does SI86SL40HC-IS1R support fail-safe output behavior during power loss?
Yes, SI86SL40HC-IS1R offers factory-selectable fail-safe mode: the output defaults to high or low when the input-side supply is unpowered but the output-side supply remains active. This behavior is defined at order time and ensures predictable state transitions in battery management fault handling.
How does the SMb pin function in SI86SL40HC-IS1R and what power savings does it enable?
The SMb pin is an active-low sleep control input that reduces SI86SL40HC-IS1R's quiescent current to 750 µA per side. When asserted, it disables all transmitter/receiver circuits except one monitoring channel - enabling rapid wake-up while cutting dynamic power in always-on BMS monitoring circuits.
What is the maximum data rate supported by SI86SL40HC-IS1R and how is timing performance characterized?
SI86SL40HC-IS1R supports up to 150 Mbps data rate with 10 ns typical propagation delay and 3.5 ns typical pulse width distortion. These values are measured at 5 V supply and –40 to 125 °C, ensuring deterministic timing for high-speed SPI, QSPI, and PWM isolation in automotive power electronics.
Is SI86SL40HC-IS1R compatible with standard SOIC-16 PCB footprints and what layout considerations apply?
SI86SL40HC-IS1R uses a WB SOIC-16 footprint with 10.3 mm body width and 1.27 mm pitch. Layout must maintain ≥8.3 mm creepage/clearance across the isolation barrier, place 0.1 µF + 10 µF bypass capacitors within 5 mm of each VDD/GND pair, and avoid routing noisy traces near GND1/GND2 pins to preserve CMTI performance.
SI86SL40HC-IS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 4/0
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 18ns, 18ns
- Pulse Width Distortion (Max):
- 7ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86SL40HC-IS1R FAQ
1.How can I place an order for SI86SL40HC-IS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86SL40HC-IS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86SL40HC-IS1R reliable?
The price and inventory of SI86SL40HC-IS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86SL40HC-IS1R is usually 5 days.
3.What payment methods are accepted for SI86SL40HC-IS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86SL40HC-IS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86SL40HC-IS1R?
SI86SL40HC-IS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86SL40HC-IS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86SL40HC-IS1R?
For technical support, including SI86SL40HC-IS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86SL40HC-IS1R requirements.
6.How does Aetrix verify that SI86SL40HC-IS1R is sourced from the original manufacturer or authorized distributors?
All SI86SL40HC-IS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86SL40HC-IS1R meets industry standards.
7.What is the process for return or replacement of SI86SL40HC-IS1R?
All SI86SL40HC-IS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI86SL40HC-IS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86SL40HC-IS1R part is unused and in its original packaging.
Return procedure for SI86SL40HC-IS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86SL40HC-IS1R Tags
-
ISO1212DBQR
Texas Instruments

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ISO6721BDR
Texas Instruments

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SI8710AC-B-ISR
Skyworks Solutions Inc.

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ISO7720FDR
Texas Instruments

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ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

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SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

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ISO7721DWVR
Texas Instruments
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ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
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