Skyworks Solutions Inc. SI86SM40BC-AS1R
- Part No.:
- SI86SM40BC-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86SM40BC-AS1R.pdf
- Description:
- 3.75 KVRMS SLEEP MODE ISOLATOR,
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86SM40BC-AS1R from Skyworks Solutions is a four-channel digital isolator with reinforced 6000 VRMS isolation, sleep mode control (SMb pin), and bidirectional signal transfer across an RF-based semiconductor barrier. It operates from 2.25 to 5.5 V on both sides, supports up to 150 Mbps data rate, and delivers 10 ns typical propagation delay. It is used in battery management systems and isolated ADC interfaces where low-power operation and fail-safe output states are required.
For engineers reviewing the SI86SM40BC-AS1R datasheet, SI86SM40BC-AS1R pinout, SI86SM40BC-AS1R application, or SI86SM40BC-AS1R equivalent, key selection criteria include its sleep-mode current (750 µA per side), reinforced IEC 60747-17 rating, AEC-Q100 qualification, and WB SOIC-16 package with 8.3 mm creepage/clearance.
Technical Context
The SI86SM40BC-AS1R implements RF-based on/off keying modulation across a monolithic semiconductor isolation barrier, eliminating startup initialization and enabling deterministic timing. Its architecture includes dedicated transmitter (HF XMTR) and receiver (HF RCVR) circuits per channel, with Schmitt-trigger inputs and CMOS thresholds for high noise immunity.
Sleep mode is controlled by the active-low SMb pin, which disables all transmitters except one monitoring channel; outputs enter tri-state when active. The device supports selectable fail-safe output state (default high/low) and features undervoltage lockout (UVLO) with 2.10–2.25 V rising threshold and 105–160 mV hysteresis on both VDD1 and VDD2 rails.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | DC to 150 Mbps - supports high-speed serial links including isolated SPI and QSPI buses |
| Isolation rating | 6000 VRMS - meets reinforced insulation requirements per UL 1577 and IEC 60747-17 |
| Propagation delay | 10 ns typical - enables precise timing-critical applications such as motor control gate drivers |
| Supply voltage | 2.25 to 5.5 V per side - allows interoperability with 3.3 V and 5 V logic domains without level shifters |
| Operating temperature | –40 to 125 °C - qualified for automotive under-hood and industrial ambient environments |
| Sleep current | 750 µA per side - reduces system power during idle periods while retaining fast wake-up capability |
| CMTI | ≥100 kV/µs - ensures robust operation in high-noise motor drive and inverter applications |
Pinout & Package
SI86SM40BC-AS1R is housed in a wide-body SOIC-16 (WB SOIC-16) package with 8.3 mm creepage and clearance, supporting 6000 VRMS isolation. Pin numbering follows standard SOIC-16 layout (pin 1 at top-left corner, counterclockwise).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Side A supply | Main-side power input (2.25–5.5 V); requires 0.1 µF + 10 µF bypass capacitors |
| A1–A4 | Side A I/O | Four bidirectional digital channels on main side; Schmitt-trigger inputs with 0.15×VDD hysteresis |
| SMb | Sleep mode control | Active-low input that places device into ultra-low-power sleep (750 µA/side) while retaining wake-up capability |
| GND1 | Side A ground | Reference for VDD1 and A-side signals; must be separated from GND2 by isolation barrier |
| Isolation Barrier | Internal die boundary | Monolithic RF-coupled semiconductor barrier; no external components needed for isolation integrity |
| B1–B4 | Side B I/O | Four isolated digital channels on secondary side; compatible with 3.3 V or 5 V logic loads |
| GND2 | Side B ground | Reference for VDD2 and B-side signals; galvanically isolated from GND1 |
| VDD2 | Side B supply | Secondary-side power input (2.25–5.5 V); independent of VDD1 for dual-supply system design |
Key Features
| Feature | Design Value |
|---|---|
| Sleep mode control | SMb pin enables hardware-controlled ultra-low-power state (750 µA/side) without sacrificing wake-up speed or channel availability |
| Reinforced safety certification | UL 1577 (6000 VRMS), VDE 60747-17, CSA 62368-1/60601-1 - eliminates need for external safety components in medical and EV systems |
| No start-up initialization | RF modulation architecture ensures immediate functional readiness after power-on; no configuration or handshake required |
| Selectable fail-safe output | Ordering option determines default output state (high or low) during unpowered conditions - critical for safe system shutdown behavior |
| High CMTI immunity | ≥100 kV/µs common-mode transient immunity - maintains signal integrity in noisy motor drive and inverter gate-drive circuits |
Applications
| Battery Management Systems (BMS) | Isolated ADC Interfaces |
|---|---|
Use Scenario: Monitoring cell voltages and temperatures in high-voltage EV battery packs with >400 V DC bus. IC Role / Device Role / Timing Role: Isolates analog front-end measurement data from MCU domain while maintaining timing coherence for SOC estimation algorithms. Use Value: Enables accurate 16-bit ADC sampling across 6000 VRMS barrier without timing skew or startup delay, meeting ASIL-B functional safety requirements. | Use Scenario: Transmitting precision sensor data from isolated current/voltage sensing circuits to host controller in industrial PLCs. IC Role / Device Role / Timing Role: Provides galvanic isolation for serial interface (e.g., SPI) between isolated sigma-delta modulator and digital filter block. Use Value: Delivers 150 Mbps throughput and 10 ns propagation delay to preserve resolution and sampling fidelity in 24-bit delta-sigma systems. |
| Motor Control Gate Drivers | Onboard Chargers (OBC) |
Use Scenario: Driving high-side and low-side IGBTs in three-phase traction inverters with fast switching and high dv/dt noise. IC Role / Device Role / Timing Role: Transfers PWM signals across isolation barrier with matched channel delays to prevent shoot-through in half-bridge configurations. Use Value: Achieves <3.5 ns pulse width distortion and ≥100 kV/µs CMTI to ensure reliable gate drive timing under 5 kV/µs transients. | Use Scenario: Isolating communication and control signals between AC/DC and DC/DC stages in bi-directional EV onboard chargers. IC Role / Device Role / Timing Role: Bridges CAN, SPI, and GPIO signals between primary-side controller and secondary-side battery interface ICs. Use Value: Supports AEC-Q100 Grade 1 qualification and –40 to 125 °C operation for continuous duty in thermally constrained OBC enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM2400ARWZ | 4-channel, 25 Mbps max data rate; 2.5 kVRMS isolation; no sleep mode pin; 16-pin SOIC package | Limited to lower-speed industrial automation; lacks AEC-Q100 qualification and reinforced insulation | Choose when cost sensitivity outweighs speed, safety, and automotive compliance requirements |
| ISO6741QDWR | 4-channel, 50 Mbps max data rate; 5 kVRMS isolation; no SMb pin; 16-pin SOIC package; TI's reinforced isolation | Suitable for industrial power supplies but not certified for automotive traction systems | Prefer for non-automotive applications requiring TI ecosystem support and lower quiescent current at reduced speed |
Compared with ADUM2400ARWZ and ISO6741QDWR, SI86SM40BC-AS1R provides 3× higher data rate, 20% greater isolation voltage, integrated sleep control, and full AEC-Q100 Grade 1 qualification - making it uniquely suited for next-generation EV battery and inverter control systems.
Availability
SI86SM40BC-AS1R is available at Aetrix Electronics and suitable for battery management systems, onboard chargers, and isolated ADC interfaces requiring stable component supply across automotive and industrial production cycles.
Supply support for SI86SM40BC-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si86Sxx family was designed specifically for high-reliability, high-speed digital isolation in automotive traction systems and industrial power conversion, emphasizing reinforced safety, low-latency timing, and ultra-low-power modes.
FAQ
What is the isolation voltage rating of SI86SM40BC-AS1R and which safety standards does it meet?
SI86SM40BC-AS1R is rated for 6000 VRMS reinforced isolation per UL 1577 and complies with IEC 60747-17, CSA 62368-1 and 60601-1, and CQC GB4943.1. This rating is validated for 1-minute withstand and supports end-equipment certifications in medical, industrial, and electric vehicle applications. The device achieves this in its WB SOIC-16 package with 8.3 mm creepage and clearance.
Does SI86SM40BC-AS1R require external configuration or initialization at power-up?
No, SI86SM40BC-AS1R requires no start-up initialization due to its RF on/off keying architecture. It begins transmitting valid data within 0.3 ms after VDD exceeds UVLO+ (2.10–2.25 V). Outputs follow inputs immediately upon stabilization, with no firmware, register writes, or handshake protocols needed - simplifying system boot sequences in automotive and industrial controllers.
How does the SMb pin function in SI86SM40BC-AS1R and what is its impact on power consumption?
The SMb pin is an active-low sleep mode control input. When pulled low, SI86SM40BC-AS1R enters sleep mode drawing only 750 µA per side while retaining one active monitoring channel for wake-up detection. When released (high or open), full operation resumes within microseconds. This feature enables dynamic power management in battery-powered or thermally constrained systems without compromising responsiveness.
What is the default output state behavior of SI86SM40BC-AS1R during power loss on the input side?
SI86SM40BC-AS1R offers ordering options for selectable fail-safe output: either default-high or default-low when VDD1 is unpowered but VDD2 remains active. This behavior is hard-coded per part number and ensures predictable system-level response during brownout or controller failure - critical for safety-critical functions like BMS fault signaling or inverter shutdown sequencing.
Can SI86SM40BC-AS1R support bidirectional communication on individual channels?
Yes, SI86SM40BC-AS1R supports true bidirectional signal transfer per channel (A1↔B1, A2↔B2, etc.) without direction control pins. Each channel operates independently in both directions simultaneously, enabled by its RF modulation architecture. This eliminates the need for external direction logic or bus transceivers in isolated UART, SMBus, or custom serial interfaces.
SI86SM40BC-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 4/0
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 42ns, 42ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86SM40BC-AS1R FAQ
1.How can I place an order for SI86SM40BC-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86SM40BC-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86SM40BC-AS1R reliable?
The price and inventory of SI86SM40BC-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86SM40BC-AS1R is usually 5 days.
3.What payment methods are accepted for SI86SM40BC-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86SM40BC-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86SM40BC-AS1R?
SI86SM40BC-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86SM40BC-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86SM40BC-AS1R?
For technical support, including SI86SM40BC-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86SM40BC-AS1R requirements.
6.How does Aetrix verify that SI86SM40BC-AS1R is sourced from the original manufacturer or authorized distributors?
All SI86SM40BC-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86SM40BC-AS1R meets industry standards.
7.What is the process for return or replacement of SI86SM40BC-AS1R?
All SI86SM40BC-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI86SM40BC-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86SM40BC-AS1R part is unused and in its original packaging.
Return procedure for SI86SM40BC-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86SM40BC-AS1R Tags
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ISO1212DBQR
Texas Instruments

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ISO6721BDR
Texas Instruments

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SI8710AC-B-ISR
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ISO7720FDR
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ISO7721DR
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ISO7721FDR
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SI8710CC-B-ISR
Skyworks Solutions Inc.

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ISO6741FQDWRQ1
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ISO7721DWVR
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ISO7762FDBQR
Texas Instruments

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ISO7741DWR
Texas Instruments

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ISO7741FDWR
Texas Instruments
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