Skyworks Solutions Inc. SI86SM40EC-AS1R
- Part No.:
- SI86SM40EC-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86SM40EC-AS1R.pdf
- Description:
- 3.75 KVRMS SLEEP MODE ISOLATOR,
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86SM40EC-AS1R from Skyworks Solutions is a 4-channel reinforced digital isolator with sleep mode control (SMb pin), 6000 VRMS isolation rating, 150 Mbps data rate, and operation across –40 to 125 °C. It features bidirectional channel configuration (A1–A4/B1–B4), Schmitt-trigger CMOS inputs, and tri-state outputs with enable-used in isolated ADC interfaces, battery management systems, and traction inverter gate driver circuits.
For engineers reviewing the SI86SM40EC-AS1R datasheet, SI86SM40EC-AS1R pinout, SI86SM40EC-AS1R application, or SI86SM40EC-AS1R equivalent, key selection criteria include its 6000 VRMS reinforced insulation per IEC 60747-17, 10 ns typical propagation delay, sleep-mode current of 750 µA per side, and WB SOIC-16 package with 8.3 mm creepage.
Technical Context
The SI86SM40EC-AS1R implements RF-based on/off keying modulation across a semiconductor isolation barrier, eliminating startup initialization and enabling robust noise immunity (100 kV/µs CMTI). Its architecture supports independent UVLO monitoring per side (VDD1/VDD2) with RSTB reset thresholds at ~1.7 V and 0.3 ms full-power start-up time.
Sleep mode is controlled via active-low SMb pin: when asserted low, it disables all transmitters except one dedicated channel for SMb state monitoring, reducing quiescent current to 750 µA per side while preserving fast wake-up capability. Channel direction is fixed (A→B forward), with no DIR pin-distinguishing it from Si86SQ44 variants.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | DC to 150 Mbps - supports high-speed SPI, isolated serial links, and real-time motor control feedback. |
| Isolation rating | 6000 VRMS (1 min) - meets reinforced insulation requirements for industrial and automotive high-voltage domains. |
| Propagation delay | 10 ns typical - enables precise timing-critical applications like gate driver synchronization and isolated ADC sampling. |
| Sleep current | 750 µA per side - reduces system standby power without sacrificing wake-up latency or isolation integrity. |
| Supply voltage | 2.25 to 5.5 V - interoperable with 3.3 V and 5 V logic families and compatible with wide-input DC-DC converters. |
| Operating temperature | –40 to 125 °C - qualified for under-hood automotive and industrial ambient environments. |
| CMTI | ≥100 kV/µs - ensures reliable operation in noisy inverter and motor drive switching environments. |
Pinout & Package
SI86SM40EC-AS1R is housed in a wide-body SOIC-16 (WB SOIC-16) package with 8.3 mm creepage and 10.3 mm clearance, supporting 6000 VRMS isolation. Pin 1 is marked with a dot; pins 1–8 are Side A (input side), pins 9–16 are Side B (output side), separated by an internal semiconductor isolation barrier.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Side A supply | 2.25–5.5 V power for input-side logic and transmitter circuits. |
| A1–A4 | Side A digital I/O | Four unidirectional input channels (A→B); CMOS/Schmitt-trigger compatible. |
| SMb | Sleep mode control | Active-low pin: drives device into 750 µA/side sleep mode; monitored continuously during sleep. |
| GND1 | Side A ground | Reference return for VDD1 and A-side signals; must be separated from GND2 by isolation barrier. |
| B1–B4 | Side B digital I/O | Four unidirectional output channels (A→B); tri-state capable via EN2 (pin 11). |
| EN2 | Side B output enable | Active-high control for B-side outputs; sets all B1–B4 to high-impedance when low. |
| GND2 | Side B ground | Reference return for VDD2 and B-side signals; galvanically isolated from GND1. |
| VDD2 | Side B supply | 2.25–5.5 V power for output-side logic and receiver circuits. |
Key Features
| Feature | Design Value |
|---|---|
| No-startup initialization | RF modulation architecture eliminates boot sequence-outputs follow inputs immediately after VDD stabilization. |
| Reinforced safety certification | IEC 60747-17, UL 1577 (6000 VRMS), CSA 62368-1/60601-1, and CQC GB4943.1 compliance for end-equipment certification. |
| Fail-safe output mode | Ordering option selects default high or low output state during VDD1 loss while VDD2 remains powered. |
| High-noise immunity | 100 kV/µs common-mode transient immunity (CMTI) and Schmitt-trigger inputs reject EMI in motor drives and inverters. |
| Low-power sleep mode | SMb pin reduces total quiescent current to 1.5 mA (750 µA per side) without disabling isolation barrier monitoring. |
Applications
| Isolated ADC Interface | Battery Management System (BMS) |
|---|---|
|
Use Scenario: Isolating analog-to-digital converter serial interface between high-voltage battery stack and low-voltage MCU. IC Role / Device Role / Timing Role: SI86SM40EC-AS1R transmits digitized cell voltage and temperature data across 6000 VRMS barrier with 10 ns timing precision. Use Value: Enables accurate, noise-immune monitoring of 48–800 V battery packs while meeting IEC 62619 functional safety requirements. |
Use Scenario: Signal isolation between MCU and isolated gate drivers in modular BMS units for EV traction batteries. IC Role / Device Role / Timing Role: SI86SM40EC-AS1R delivers PWM and fault feedback across reinforced barrier with <10 ns skew between channels. Use Value: Supports ASIL-C compliant diagnostics and prevents ground-loop-induced false trips in multi-module battery stacks. |
| Traction Inverter Control | Industrial PLC I/O Module |
|
Use Scenario: Isolating control signals from controller to three-phase IGBT/SiC gate drivers in electric vehicle inverters. IC Role / Device Role / Timing Role: SI86SM40EC-AS1R carries dead-time-controlled PWM and DESAT feedback with 100 kV/µs CMTI immunity. Use Value: Prevents misfiring during high dv/dt switching events (≥50 V/ns) and maintains safe shutdown response within 100 ns. |
Use Scenario: Isolating digital inputs/outputs in programmable logic controller backplane modules interfacing with field sensors and actuators. IC Role / Device Role / Timing Role: SI86SM40EC-AS1R provides four independent 150 Mbps channels for status reporting and command execution. Use Value: Eliminates ground potential differences across distributed I/O racks and supports 24 V DC field bus compatibility. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SI86SM41EC-AS1R | Same package and pinout; differs only in fail-safe default output (high vs. low on VDD1 loss). | Used where isolated outputs must assert high during controller power loss (e.g., safety interlock activation). | Select SI86SM40EC-AS1R when default-low fail-safe behavior is required for safe shutdown states. |
| ADUM4160BRIZ | 4-channel, 50 Mbps, 2500 VRMS, no sleep mode, 16-lead SOIC; higher propagation delay (32 ns). | Targeted at USB isolation and lower-speed industrial comms-not suitable for >100 Mbps or automotive AEC-Q100 designs. | Choose SI86SM40EC-AS1R for 150 Mbps, 6000 VRMS, AEC-Q100, and sleep-mode power optimization. |
Compared with SI86SM41EC-AS1R, SI86SM40EC-AS1R provides identical performance and packaging but guarantees default-low output during input-side power loss-critical for fail-safe gate driver disable. Versus ADUM4160BRIZ, it doubles data rate, triples isolation voltage, adds sleep mode, and meets automotive qualification.
Availability
SI86SM40EC-AS1R is available at Aetrix Electronics and suitable for battery management systems, traction inverters, and isolated ADC interfaces requiring stable component supply across automotive and industrial production lifecycles.
Supply support for SI86SM40EC-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si86Sxx family-including SI86SM40EC-AS1R-is engineered for high-reliability isolation in automotive electrification and industrial automation, emphasizing reinforced safety, ultra-low power sleep, and noise-immune high-speed data transfer.
FAQ
What is the isolation voltage rating of the SI86SM40EC-AS1R and which safety standards does it meet?
The SI86SM40EC-AS1R is rated for 6000 VRMS isolation for 1 minute per UL 1577 and carries reinforced insulation certification per IEC 60747-17, CSA 62368-1/60601-1, and CQC GB4943.1. This enables use in high-voltage domains such as EV battery packs and industrial motor drives where creepage and working voltage margins are critical. The WB SOIC-16 package provides 8.3 mm creepage to support these ratings.
How does the SMb pin function in the SI86SM40EC-AS1R, and what is its impact on power consumption?
The SMb pin is an active-low sleep mode control input. When driven low, SI86SM40EC-AS1R enters sleep mode with total quiescent current reduced to 1.5 mA (750 µA per side), while retaining one always-on channel to monitor SMb state. Release of SMb (high or open) restores full operation within microseconds-enabling dynamic power gating in battery-powered BMS and portable test equipment.
Does the SI86SM40EC-AS1R support bidirectional data flow, and how is channel direction configured?
No-SI86SM40EC-AS1R is a unidirectional 4-channel isolator with fixed A→B signal flow (A1–A4 to B1–B4). It lacks a DIR pin or reversible channel architecture. For bidirectional QSPI isolation, Skyworks offers the Si86SQ44. SI86SM40EC-AS1R is optimized for point-to-point isolated control and feedback paths where direction is static and timing precision is paramount.
What are the key timing specifications of the SI86SM40EC-AS1R, and how do they affect system design?
SI86SM40EC-AS1R delivers 10 ns typical propagation delay, 3.5 ns pulse width distortion, and <1 ns channel-to-channel skew. These values enable tight synchronization in gate driver control loops and isolated ADC sampling clocks. Designers can eliminate external delay compensation and reduce jitter budgets in real-time motor control and power conversion systems using SI86SM40EC-AS1R.
Is the SI86SM40EC-AS1R qualified for automotive applications, and what evidence supports this claim?
Yes-SI86SM40EC-AS1R is AEC-Q100 qualified for Grade 1 (–40 to 125 °C) operation. It is manufactured using automotive-specific process flows, supports AIAG-compliant PPAP documentation, and is listed in IMDS/CAMDS. Its 6000 VRMS rating, 100 kV/µs CMTI, and fail-safe output modes align with ISO 26262 ASIL-C requirements for onboard chargers and traction inverters.
SI86SM40EC-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 4/0
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 42ns, 42ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86SM40EC-AS1R FAQ
1.How can I place an order for SI86SM40EC-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86SM40EC-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86SM40EC-AS1R reliable?
The price and inventory of SI86SM40EC-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86SM40EC-AS1R is usually 5 days.
3.What payment methods are accepted for SI86SM40EC-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86SM40EC-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86SM40EC-AS1R?
SI86SM40EC-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86SM40EC-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86SM40EC-AS1R?
For technical support, including SI86SM40EC-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86SM40EC-AS1R requirements.
6.How does Aetrix verify that SI86SM40EC-AS1R is sourced from the original manufacturer or authorized distributors?
All SI86SM40EC-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86SM40EC-AS1R meets industry standards.
7.What is the process for return or replacement of SI86SM40EC-AS1R?
All SI86SM40EC-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI86SM40EC-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86SM40EC-AS1R part is unused and in its original packaging.
Return procedure for SI86SM40EC-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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