Skyworks Solutions Inc. SI86SM41BC-IS1R
- Part No.:
- SI86SM41BC-IS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86SM41BC-IS1R.pdf
- Description:
- 6.0 KVRMS LOW POWER ISOLATOR, 4
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86SM41BC-IS1R from Skyworks Solutions is a four-channel reinforced digital isolator with sleep mode control (SMb pin), 150 Mbps data rate, 10 ns typical propagation delay, and 6000 VRMS isolation rating. It features bidirectional channel configuration (2 forward + 2 reverse), Schmitt-trigger CMOS inputs, and operates across –40 to 125 °C for use in isolated motor control gate drivers and battery management system signal interfaces.
For engineers reviewing the SI86SM41BC-IS1R datasheet, SI86SM41BC-IS1R pinout, SI86SM41BC-IS1R application, or SI86SM41BC-IS1R equivalent, key selection criteria include its sleep-mode power reduction (750 µA per side), fail-safe default-low output option, reinforced IEC 60747-17 certification, and WB SOIC-16 package with 8.3 mm creepage.
Technical Context
The SI86SM41BC-IS1R implements RF-based on/off keying modulation across a semiconductor isolation barrier, eliminating startup initialization and enabling robust noise immunity (100 kV/µs CMTI). Its architecture supports independent UVLO monitoring per side (VDD1/VDD2) with RSTB reset thresholds (~1.7 V) and configurable fail-safe output states during unpowered conditions.
Sleep mode is controlled via the active-low SMb pin: when pulled low, it places all transmitters and receivers into ultra-low-power state while retaining one always-on channel to monitor SMb status. Outputs enter high-impedance state, and device restarts automatically upon SMb release or high transition.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | DC to 150 Mbps - supports high-speed SPI, isolated ADC/DAC interfaces, and real-time motor control feedback loops. |
| Propagation delay | 10 ns typical - enables precise timing alignment in closed-loop power converter control and fast-response safety systems. |
| Isolation rating | 6000 VRMS (1 min) - meets reinforced insulation requirements for industrial inverters and EV traction systems per UL 1577 and VDE 60747-17. |
| Supply voltage | 2.25–5.5 V - allows direct interface with 3.3 V and 5 V logic domains without level-shifting circuitry. |
| Operating temperature | –40 to 125 °C - qualified for under-hood automotive and industrial ambient environments without derating. |
| Sleep current | 750 µA per side - reduces standby power in battery-backed BMS and portable medical equipment. |
| Pulse width distortion | 3.5 ns typical - preserves signal integrity in high-frequency PWM and encoder signal isolation. |
Pinout & Package
The SI86SM41BC-IS1R is housed in a wide-body SOIC-16 (WB SOIC-16) package with 8.3 mm creepage and 10.3 mm clearance, supporting 6000 VRMS reinforced isolation. Pin numbering follows standard SOIC-16 layout with isolation barrier between pins 1–8 (Side A) and 9–16 (Side B).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1, GND1 | Side A supply | Power and ground for input-side logic (e.g., MCU GPIO, SPI controller); requires 0.1 µF + 10 µF bypassing. |
| A1–A4 | Side A digital I/O | Four bidirectional channels: A1/A2 forward, A3/A4 reverse - configurable via external direction logic or fixed per variant. |
| SMb | Sleep mode enable | Active-low pin controlling full-device sleep; internal pull-up ensures wake-on-release behavior. |
| VDD2, GND2 | Side B supply | Independent isolated power domain for gate drivers, sensors, or secondary controllers. |
| B1–B4 | Side B digital I/O | Corresponding isolated outputs/inputs mirroring A1–A4; high-impedance when SMb = low. |
| NC | No connect | Pin 15 is not bonded - must remain unconnected per design; no routing or thermal tie allowed. |
Key Features
| Feature | Design Value |
|---|---|
| Sleep mode with SMb control | Reduces quiescent current to 750 µA/side while retaining wake capability - eliminates need for external power gating in always-on systems. |
| Reinforced IEC 60747-17 rating | Validated for functional safety-critical applications including ISO 26262 ASIL-B automotive subsystems and IEC 61508 SIL-2 industrial controls. |
| Fail-safe default-low output | Ensures predictable low-state outputs during VDD1/VDD2 brownout - critical for preventing unintended activation of MOSFET/IGBT gate drivers. |
| 100 kV/µs CMTI immunity | Withstands rapid common-mode transients in noisy motor drive and inverter environments without data corruption or latch-up. |
| Schmitt-trigger + CMOS inputs | Provides 0.15 × VDDx hysteresis and noise margin up to 30% of supply - rejects EFT bursts and radiated RFI in industrial enclosures. |
Applications
| Motor Control Gate Driver Interface | Isolated Battery Management System |
|---|---|
|
Use Scenario: Isolating PWM signals and fault feedback between MCU and three-phase inverter gate drivers in servo drives. IC Role / Device Role / Timing Role: Four-channel isolator transmitting gate enable/disable commands (A1–A2) and receiving desaturation/fault signals (B3–B4) with <10 ns timing skew. Use Value: Enables safe, high-fidelity switching at >20 kHz carrier frequencies while meeting reinforced insulation requirements for 600 V DC bus systems. |
Use Scenario: Signal isolation between cell monitor ICs and main BMS microcontroller in EV battery packs. IC Role / Device Role / Timing Role: Transferring voltage/temperature readings and cell balancing commands across isolation barrier with fail-safe low-default during partial power loss. Use Value: Prevents false triggering of balancing FETs during transient VDD dips, improving pack reliability and reducing thermal runaway risk. |
| Industrial PLC Digital I/O Module | Medical Isolated Data Acquisition |
|
Use Scenario: Providing channel-isolated 24 V DC input sensing and relay driver outputs in modular PLC backplanes. IC Role / Device Role / Timing Role: Bidirectional isolation of status inputs (A1–A2) and control outputs (B3–B4) with tri-state capability during hot-swap events. Use Value: Eliminates ground loop errors and enables safe field wiring without external optocouplers or discrete isolation components. |
Use Scenario: Isolating analog front-end ADC/DAC control lines and interrupt signals in patient-connected diagnostic equipment. IC Role / Device Role / Timing Role: Transmitting SPI clock/data between isolated ADC and host processor while maintaining 6000 VRMS patient-side barrier integrity. Use Value: Meets reinforced insulation requirements of IEC 60601-1 for Type BF applied parts without compromising sampling throughput. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM2401ARWZ | 4-channel, 1 Mbps max data rate, 50 ns propagation delay, 2500 VRMS isolation, no sleep mode. | Lower speed and isolation rating limit use to non-safety-critical industrial I/O, not suitable for EV traction inverters. | Choose ADUM2401ARWZ only for cost-sensitive, low-speed legacy designs where 150 Mbps and 6000 VRMS are unnecessary. |
| ISO7741FDWR | 4-channel, 100 Mbps, 11 ns propagation delay, 5000 VRMS, no SMb pin, different pinout (SOIC-16 NB). | Lacks sleep mode and has lower isolation - acceptable for industrial automation but not automotive AEC-Q100-compliant systems. | Select ISO7741FDWR when board space constraints favor narrow-body SOIC-16 and sleep mode is not required. |
Compared with ADUM2401ARWZ and ISO7741FDWR, the SI86SM41BC-IS1R delivers 150× higher data rate than the former and 50% higher isolation voltage than the latter, while uniquely integrating sleep mode for energy-constrained battery systems - making it the only option qualified for AEC-Q100 Grade 0 automotive applications among the three.
Availability
SI86SM41BC-IS1R is available at Aetrix Electronics and suitable for industrial motor control, automotive battery management, and medical data acquisition requiring stable component supply and long-term lifecycle support.
Supply support for SI86SM41BC-IS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si86Sxx family was designed specifically for high-reliability, high-speed digital isolation in safety-critical automotive and industrial systems - emphasizing reinforced insulation, AEC-Q100 qualification, and ultra-low-power sleep operation.
FAQ
What is the isolation voltage rating and safety certification status of the SI86SM41BC-IS1R?
The SI86SM41BC-IS1R is rated for 6000 VRMS isolation per UL 1577 (1 minute) and carries reinforced insulation certification per VDE 60747-17 and CSA 62368-1. It is pending CQC GB4943.1 approval. These ratings are validated for the WB SOIC-16 package and apply directly to the SI86SM41BC-IS1R without derating.
Does the SI86SM41BC-IS1R support bidirectional data flow, and how is channel direction configured?
Yes, the SI86SM41BC-IS1R supports two forward (A→B) and two reverse (B→A) channels. Direction is fixed by internal configuration - no external DIR pin is present. The SI86SM41BC-IS1R variant is specifically ordered with this 2+2 bidirectional mapping, distinct from unidirectional or QSPI variants like Si86SQ44.
How does the SMb pin function in the SI86SM41BC-IS1R, and what happens to outputs during sleep?
The SMb pin is an active-low sleep enable. When driven low, the SI86SM41BC-IS1R enters sleep mode drawing 750 µA per side; all outputs go high-impedance and transmitters disable. One internal channel remains active to monitor SMb, allowing automatic wake-up when SMb is released or pulled high.
What is the default output state of the SI86SM41BC-IS1R during power loss, and is it configurable?
The SI86SM41BC-IS1R is ordered with default-low fail-safe behavior: when VDD1 is unpowered but VDD2 remains active, outputs B1–B4 hold logic low. This ordering option is fixed per part number - the SI86SM41BC-IS1R does not support field-selectable high/low defaults.
What bypass capacitors are required for stable operation of the SI86SM41BC-IS1R?
The SI86SM41BC-IS1R requires 0.1 µF ceramic + 10 µF bulk capacitors placed between VDD1/GND1 and VDD2/GND2, each located within 5 mm of the respective pins. This dual-capacitor network suppresses both high-frequency switching noise and low-frequency supply droop, ensuring reliable RF modulation performance.
SI86SM41BC-IS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- General Purpose
- Isolated Power:
- No
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 3/1
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 6000Vrms
- Common Mode Transient Immunity (Min):
- 100kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 14ns, 14ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86SM41BC-IS1R FAQ
1.How can I place an order for SI86SM41BC-IS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86SM41BC-IS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86SM41BC-IS1R reliable?
The price and inventory of SI86SM41BC-IS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86SM41BC-IS1R is usually 5 days.
3.What payment methods are accepted for SI86SM41BC-IS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86SM41BC-IS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86SM41BC-IS1R?
SI86SM41BC-IS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86SM41BC-IS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86SM41BC-IS1R?
For technical support, including SI86SM41BC-IS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86SM41BC-IS1R requirements.
6.How does Aetrix verify that SI86SM41BC-IS1R is sourced from the original manufacturer or authorized distributors?
All SI86SM41BC-IS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86SM41BC-IS1R meets industry standards.
7.What is the process for return or replacement of SI86SM41BC-IS1R?
All SI86SM41BC-IS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI86SM41BC-IS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86SM41BC-IS1R part is unused and in its original packaging.
Return procedure for SI86SM41BC-IS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86SM41BC-IS1R Tags
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ISO1212DBQR
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ISO6721BDR
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SI8710AC-B-ISR
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ISO7720FDR
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ISO7721DR
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ISO7721FDR
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SI8710CC-B-ISR
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ISO6741FQDWRQ1
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ISO7721DWVR
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ISO7762FDBQR
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ISO7741DWR
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ISO7741FDWR
Texas Instruments
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