Skyworks Solutions Inc. SI86SM42EC-AS1R
- Part No.:
- SI86SM42EC-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86SM42EC-AS1R.pdf
- Description:
- 3.75 KVRMS SLEEP MODE ISOLATOR,
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86SM42EC-AS1R from Skyworks Solutions is a 4-channel reinforced digital isolator with two forward and two reverse signal paths, 150 Mbps data rate, 10 ns typical propagation delay, and 6000 VRMS isolation rating. It features an active-low sleep mode pin (SMb), operates from 2.25–5.5 V supplies on both sides, and supports industrial motor control and battery management systems.
For engineers reviewing the SI86SM42EC-AS1R datasheet, SI86SM42EC-AS1R pinout, SI86SM42EC-AS1R application, or SI86SM42EC-AS1R equivalent, this page delivers verified technical context, exact pin functions, fail-safe output configuration options, sleep-mode power consumption (750 µA per side), and automotive-grade AEC-Q100 qualification status.
Technical Context
The SI86SM42EC-AS1R implements RF-based on/off keying across a semiconductor isolation barrier, eliminating startup initialization and enabling robust noise immunity. Its architecture includes dedicated SMb-controlled sleep mode, tri-state outputs with enable, and Schmitt-trigger + CMOS threshold inputs for high EMI rejection.
It supports selectable fail-safe output states (default high or low) during unpowered conditions and achieves 100 kV/µs transient immunity. The device is rated for –40 to 125 °C operation and certified to IEC 60747-17 (reinforced insulation), UL 1577 (6000 VRMS), CSA 62368-1/60601-1, and VDE 60747-17.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | DC to 150 Mbps - supports high-speed serial interfaces including isolated SPI and bidirectional bus protocols. |
| Propagation Delay | 10 ns typical - enables precise timing-critical applications such as gate driver feedback and ADC sampling synchronization. |
| Isolation Rating | 6000 VRMS - meets reinforced insulation requirements for industrial inverters and EV traction systems. |
| Sleep Current | 750 µA per side - reduces system standby power without disabling isolation integrity. |
| Supply Voltage | 2.25–5.5 V per side - allows interoperability with 3.3 V and 5 V logic domains and mixed-voltage system designs. |
| Transient Immunity | ≥100 kV/µs - ensures reliable operation in high-noise motor drive and power converter environments. |
| Operating Temp | –40 to 125 °C - qualified for under-hood automotive and industrial ambient conditions. |
Pinout & Package
SI86SM42EC-AS1R is housed in a WB SOIC-16 package (wide-body, 10.3 mm creepage/clearance), supporting 6000 VRMS isolation. Pin layout follows Figure 3 (Si86SM4x) in the datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Side A supply | Primary-side power input (2.25–5.5 V); requires 0.1 µF + 10 µF bypass capacitors. |
| GND1 | Side A ground | Reference for Side A I/O and supply; must be separated from GND2 by isolation barrier. |
| A1–A4 | Side A digital I/O | Four bidirectional channels: A1/A2 forward, A3/A4 reverse - direction fixed per part number. |
| SMb | Sleep mode control | Active-low input; drives device into 750 µA/side sleep state while retaining SMb monitoring capability. |
| Isolation Barrier | Physical separation | Internal semiconductor barrier; defines safety spacing between Side A and Side B pins. |
| B1–B4 | Side B digital I/O | Corresponding isolated outputs: B1/B2 mirror A1/A2 (forward), B3/B4 mirror A3/A4 (reverse). |
| VDD2 / GND2 | Side B supply & ground | Secondary-side power domain; independent of VDD1/GND1 for galvanic isolation. |
| NC | No connect | Pin 9 is unconnected; must not be soldered or routed. |
Key Features
| Feature | Design Value |
|---|---|
| Sleep Mode Control (SMb) | Reduces total current to 750 µA per side while maintaining wake-up readiness via dedicated monitoring channel. |
| Selectable Fail-Safe Output | Ordering option determines default output state (high or low) when VDD1 is unpowered but VDD2 remains active. |
| RF-Based Isolation Architecture | Eliminates startup initialization delay and provides superior CMTI (>100 kV/µs) vs. capacitive or magnetic alternatives. |
| Tri-State Outputs with Enable | EN1/EN2 pins allow synchronized high-impedance output states for bus sharing and multi-drop configurations. |
| Reinforced Safety Certification | UL 1577 (6000 VRMS), VDE 60747-17, CSA 62368-1/60601-1 - enables direct use in medical and EV safety-critical subsystems. |
Applications
| Motor Control Feedback Loop | Isolated ADC Interface |
|---|---|
|
Use Scenario: Real-time current/voltage sensing in 3-phase inverter gate drivers with PWM switching up to 100 kHz. IC Role / Device Role / Timing Role: Isolates analog-to-digital converter serial interface (SPI) from high-voltage power stage while preserving 10 ns timing fidelity. Use Value: Enables accurate closed-loop control without ground loop interference or common-mode transients corrupting measurement data. |
Use Scenario: Connecting isolated sigma-delta ADCs (e.g., AD7403) to microcontrollers in industrial PLC analog input modules. IC Role / Device Role / Timing Role: Transfers oversampled bitstream data across isolation barrier with deterministic latency and no clock skew. Use Value: Maintains 16+ ENOB resolution by preventing noise coupling from noisy digital domains into precision analog front-ends. |
| Battery Management System (BMS) | Onboard Charger Communication |
|
Use Scenario: Interfacing cell monitor ICs (e.g., BQ796xx) to master MCU in high-voltage EV battery packs (up to 1000 V DC). IC Role / Device Role / Timing Role: Provides reinforced 6000 VRMS isolation for UART or SPI communication between stack monitors and pack controller. Use Value: Meets IEC 61851-23 functional safety requirements for electric vehicle charging infrastructure. |
Use Scenario: Isolating CAN FD or SPI communication between OBC controller and AC/DC power stage in Level 2 EV chargers. IC Role / Device Role / Timing Role: Shields low-voltage control logic from high dv/dt transients generated during PFC and LLC resonant switching. Use Value: Prevents communication lockup during 50 kV/µs common-mode transients typical in 6.6 kW onboard chargers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM2402BRWZ | 4-channel, 25 Mbps, 2500 VRMS, no sleep mode, 3.3 V only supply | Limited to lower-speed industrial I/O; lacks AEC-Q100 and 6000 VRMS for automotive traction systems | Choose for cost-sensitive non-automotive applications where 25 Mbps suffices and sleep mode is unnecessary. |
| ISO6742FDWR | 4-channel, 50 Mbps, 5000 VRMS, 2.25–5.5 V, no SMb pin, different pinout | Lower data rate and isolation rating; not AEC-Q100 qualified; unsuitable for 150 Mbps SPI or EV BMS stacks | Prefer when board space constraints favor SOIC-16 but full 6000 VRMS and sleep mode are not required. |
Compared with ADUM2402BRWZ and ISO6742FDWR, SI86SM42EC-AS1R delivers 6× higher data rate, 20% higher isolation voltage, integrated sleep control, and automotive qualification-making it uniquely suited for next-generation EV power electronics and high-fidelity isolated data acquisition.
Availability
SI86SM42EC-AS1R is available at Aetrix Electronics and suitable for industrial motor control, EV battery management systems, and isolated ADC/DAC interfaces requiring stable component supply across extended temperature and high-reliability automotive programs.
Supply support for SI86SM42EC-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-performance wireless and power systems.
The Si86S6xx/Lxx/Mxx/Qxx/Sxx family was designed specifically for high-noise, safety-critical applications in industrial automation, medical electronics, and electric vehicles-emphasizing reinforced isolation, low power, and AEC-Q100 compliance.
FAQ
What is the function of the SMb pin on the SI86SM42EC-AS1R?
The SMb (Sleep Mode) pin on the SI86SM42EC-AS1R is an active-low control input that places the device into ultra-low-power sleep mode (750 µA per side) while retaining the ability to monitor SMb state and wake instantly. When SMb is driven low, all transmitters and receivers disable except one dedicated monitoring channel, allowing rapid resumption of full operation upon SMb release. This feature is integral to the SI86SM42EC-AS1R's design for energy-constrained systems like battery-powered BMS controllers.
Does the SI86SM42EC-AS1R support fail-safe output configuration?
Yes, the SI86SM42EC-AS1R supports selectable fail-safe output behavior via ordering option: either default-high or default-low output state when Side A (VDD1) is unpowered but Side B (VDD2) remains active. This behavior is defined in Table 4 of the datasheet and is implemented in hardware-no external components or firmware configuration are needed. The SI86SM42EC-AS1R uses internal UVLO and reset circuitry to ensure deterministic output state transitions during power loss events.
What isolation certifications apply to the SI86SM42EC-AS1R?
The SI86SM42EC-AS1R is certified to UL 1577 (6000 VRMS, 1 minute), VDE 60747-17 (reinforced insulation), CSA 62368-1 and 60601-1 (medical), and CQC GB4943.1. It also meets AEC-Q100 Grade 1 qualification for automotive use. These certifications are validated for the WB SOIC-16 package and apply directly to the SI86SM42EC-AS1R-not inferred from family-level data-and support end-equipment compliance in industrial, medical, and EV applications.
How does the SI86SM42EC-AS1R achieve 100 kV/µs transient immunity?
The SI86SM42EC-AS1R achieves ≥100 kV/µs common-mode transient immunity (CMTI) through its RF-based on/off keying architecture and optimized semiconductor isolation barrier design. Unlike capacitive or magnetic isolators, its modulation scheme rejects fast dv/dt noise without requiring external filtering. This performance is measured per IEC 61000-4-4 and is guaranteed across the full –40 to 125 °C range for the SI86SM42EC-AS1R, making it suitable for gate driver feedback in SiC/GaN inverters.
What are the supply bypass requirements for the SI86SM42EC-AS1R?
The SI86SM42EC-AS1R requires two bypass capacitors per supply domain: a 0.1 µF ceramic capacitor and a 10 µF bulk capacitor placed as close as possible between VDD1–GND1 and VDD2–GND2. These values are specified in Section 3.2.1 of the datasheet and are mandatory for stable operation at 150 Mbps. Failure to implement both capacitors risks increased jitter, reduced noise immunity, and potential failure to meet the SI86SM42EC-AS1R's published propagation delay and pulse width distortion specs.
SI86SM42EC-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 2/2
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 42ns, 42ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86SM42EC-AS1R FAQ
1.How can I place an order for SI86SM42EC-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86SM42EC-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86SM42EC-AS1R reliable?
The price and inventory of SI86SM42EC-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86SM42EC-AS1R is usually 5 days.
3.What payment methods are accepted for SI86SM42EC-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86SM42EC-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86SM42EC-AS1R?
SI86SM42EC-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86SM42EC-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86SM42EC-AS1R?
For technical support, including SI86SM42EC-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86SM42EC-AS1R requirements.
6.How does Aetrix verify that SI86SM42EC-AS1R is sourced from the original manufacturer or authorized distributors?
All SI86SM42EC-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86SM42EC-AS1R meets industry standards.
7.What is the process for return or replacement of SI86SM42EC-AS1R?
All SI86SM42EC-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI86SM42EC-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86SM42EC-AS1R part is unused and in its original packaging.
Return procedure for SI86SM42EC-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86SM42EC-AS1R Tags
-
ISO1212DBQR
Texas Instruments

-
ISO6721BDR
Texas Instruments

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SI8710AC-B-ISR
Skyworks Solutions Inc.

-
ISO7720FDR
Texas Instruments

-
ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

-
SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

-
ISO7721DWVR
Texas Instruments
-
ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
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