Skyworks Solutions Inc. SI86SO21BC-ASR
- Part No.:
- SI86SO21BC-ASR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86SO21BC-ASR.pdf
- Description:
- 3.75 KVRMS INVERTING OUTPUT ISOL
- Quantity:
- Payment:

- Shipping:

Inventory:1,300
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Product details
Overview
SI86SO21BC-ASR from Skyworks Solutions is a dual-channel, high-speed digital isolator with reinforced 6000 VRMS isolation, AEC-Q100 qualified for automotive use, and featuring inverting logic outputs, 150 Mbps data rate, and fail-safe default-low operation. It enables isolated communication between microcontrollers and gate drivers in traction inverters and battery management systems.
For engineers reviewing the SI86SO21BC-ASR datasheet, SI86SO21BC-ASR pinout, SI86SO21BC-ASR application, or SI86SO21BC-ASR equivalent, this page delivers verified timing specs (9 ns typical propagation delay), CMTI (100 kV/µs), supply range (2.25–5.5 V), and automotive-grade safety certifications (VDE 60747-17, UL 1577) critical for high-reliability power electronics design.
Technical Context
The SI86SO21BC-ASR implements RF-based on/off keying across a semiconductor isolation barrier-eliminating start-up initialization and providing superior noise immunity over pulse-width or capacitive schemes. Its architecture includes independent UVLO and reset circuits per side (VDD1/VDD2), with RSTB thresholds at ~1.7 V and UVLO hysteresis of 131 mV.
It supports selectable fail-safe mode via ordering option: SI86SO21BC-ASR is configured for default-low output during input-side power loss, enforced by internal pulldown resistors on both A1/A2 and B1/B2 I/Os. The device operates across –40 to +125 °C with 2.25–5.5 V supplies and requires only 0.1 µF + 10 µF bypass capacitors per side.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | 150 Mbps - supports high-speed SPI, CAN FD, and PWM feedback loops without timing bottlenecks. |
| Propagation delay | 9 ns typical - enables tight timing control in motor control gate drive synchronization. |
| Isolation rating | 6000 VRMS - meets reinforced insulation requirements for 1000 V DC bus systems per UL 1577. |
| CMTI | 100 kV/µs - prevents false triggering in high-dV/dt environments like SiC/GaN inverter switching nodes. |
| Supply voltage | 2.25–5.5 V - interoperable with 3.3 V MCU logic and 5 V analog subsystems without level shifters. |
| Operating temperature | –40 to +125 °C - qualified for under-hood automotive placement per AEC-Q100 Grade 1. |
| Output configuration | Inverting - matches legacy optocoupler logic polarity in existing BMS and OBC designs. |
| Fail-safe mode | Default-low - ensures safe shutdown state when primary controller loses power in traction inverter applications. |
Pinout & Package
SI86SO21BC-ASR uses an NB SOIC-8 package (3.9 mm creepage/clearance) with reinforced insulation barrier separating Side A (VDD1/GND1/A1/A2) and Side B (VDD2/GND2/B1/B2). Pin 3 (A2) and Pin 6 (B1) are functional I/Os; Pin 4 is NC and must remain unconnected.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Side A power supply | Supplies isolated input-side logic; must be decoupled with 0.1 µF + 10 µF capacitors placed near pin. |
| GND1 | Side A ground reference | Return path for A1/A2 signals; must be separated from GND2 by ≥3.9 mm PCB clearance. |
| A1, A2 | Side A digital inputs | Inverting inputs accepting CMOS/Schmitt-trigger logic; internally pulled down for default-low fail-safe behavior. |
| NC | No-connect terminal | Pin 4 is unconnected die pad-must be left floating or grounded per layout best practices (not tied to signal). |
| GND2 | Side B ground reference | Return path for B1/B2 outputs; galvanically isolated from GND1; defines secondary-side noise floor. |
| B1, B2 | Side B digital outputs | Inverting outputs driving gate drivers or ADCs; 50 Ω nominal impedance requires controlled-impedance routing. |
| VDD2 | Side B power supply | Supplies isolated output-side circuitry; independent regulation allows different voltage domains on each side. |
Key Features
| Feature | Design Value |
|---|---|
| RF modulation architecture | Eliminates boot-time initialization delay and enables immediate data transmission upon power-up (tSTART ≤ 300 µs). |
| Reinforced insulation | 6000 VRMS withstand per UL 1577 and VDE 60747-17-certified for 2 MOPP patient protection and 1500 VRMS working voltage in SSO-8 variant. |
| High CMTI | 100 kV/µs common-mode transient immunity ensures reliable operation in 1200 V SiC inverter half-bridges. |
| Fail-safe default-low | Internal pulldowns on all I/O pins force B1/B2 low during VDD1 undervoltage-prevents unintended gate turn-on in motor drives. |
| AEC-Q100 qualification | Grade 1 (–40 to +125 °C) qualification with PPAP documentation support-meets automotive production traceability and defectivity requirements. |
| Low power consumption | 1.05 mA typical IDD1 at 5 V/500 kHz-reduces thermal load in densely packed BMS modules. |
Applications
| Onboard Charger (OBC) | Battery Management System (BMS) |
|---|---|
|
Use Scenario: Isolating 3.3 V MCU SPI commands from 400–800 V DC-link gate drivers in bidirectional AC/DC converters. IC Role / Device Role / Timing Role: Dual-channel isolator transmitting PWM enable/disable and fault feedback with <9 ns propagation delay skew. Use Value: Prevents latch-up during fast dV/dt transients (≥100 kV/µs) while maintaining <10 ns channel-to-channel skew for synchronous gate switching. |
Use Scenario: Isolating cell monitor IC UART lines from main MCU in high-voltage battery packs (up to 900 V). IC Role / Device Role / Timing Role: Inverting isolator relaying thermistor and voltage readings with fail-safe low output during MCU brownout. Use Value: Ensures cell monitoring remains disabled during power loss-avoiding erroneous balancing commands that could cause thermal runaway. |
| Traction Inverter | Charging Station Power Stack |
|
Use Scenario: Transmitting isolated gate drive signals to SiC half-bridge modules operating at 100 kHz switching frequency. IC Role / Device Role / Timing Role: Dual-channel isolator delivering complementary PWM with precise 9 ns typical tPHL/tPLH for dead-time control. Use Value: Enables <15 ns total propagation uncertainty-critical for minimizing shoot-through risk in 1200 V SiC systems. |
Use Scenario: Isolating digital control signals between primary-side PFC controller and secondary-side LLC resonant controller in 20 kW+ EVSE units. IC Role / Device Role / Timing Role: Reinforced 6000 VRMS isolator bridging 1000 V DC bus domains with certified 2 MOPP patient protection. Use Value: Meets IEC 62368-1 and 60601-1 requirements for public-access charging infrastructure without external safety components. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM121N0BRZ-RL7 | Single-channel, 150 Mbps, 3000 VRMS isolation, non-AEC-Q100, default-high output. | Lacks dual-channel integration and automotive qualification; insufficient for BMS cell monitoring + gate drive co-location. | Use only where single-channel isolation suffices and automotive qualification is not required. |
| ISO7721DR | Dual-channel, 100 Mbps, 5000 VRMS, no AEC-Q100, default-high output, higher 13 ns propagation delay. | Lower CMTI (85 kV/µs) and no reinforced certification for 2 MOPP-unsuitable for medical-grade or traction inverter use. | Select when cost sensitivity outweighs need for 150 Mbps speed and 6000 VRMS reinforced isolation. |
Compared with ADUM121N0BRZ-RL7 and ISO7721DR, SI86SO21BC-ASR uniquely combines dual-channel 150 Mbps operation, AEC-Q100 Grade 1 qualification, 6000 VRMS reinforced isolation, and default-low fail-safe behavior-making it the only drop-in solution for automotive traction inverter gate drive and BMS signal isolation where safety-critical shutdown behavior is mandated.
Availability
SI86SO21BC-ASR is available at Aetrix Electronics and suitable for onboard chargers, battery management systems, traction inverters, and charging station power stacks requiring stable component supply across automotive and industrial production cycles.
Supply support for SI86SO21BC-ASR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-performance wireless and power systems.
The Si86S61x/S62x/SOx family was designed specifically for automotive and industrial isolation applications demanding AEC-Q100 qualification, reinforced safety certification, and high-speed robustness in noisy high-voltage environments-exemplified by SI86SO21BC-ASR's dual-channel, inverting, default-low architecture.
FAQ
What is the isolation voltage rating of SI86SO21BC-ASR and which safety standards does it meet?
SI86SO21BC-ASR provides 6000 VRMS isolation per UL 1577 and is certified to VDE 60747-17 (reinforced), CSA 62368-1, and CQC GB4943.1. It supports up to 1500 VRMS working voltage in SSO-8 packages and 445 VRMS in NB SOIC-8-validated for 2 MOPP in medical and automotive applications. SI86SO21BC-ASR meets these ratings without external components.
Does SI86SO21BC-ASR require external startup initialization or configuration?
No-SI86SO21BC-ASR uses RF-based on/off keying with no firmware or register programming needed. It begins transmitting valid data within 300 µs of VDD1/VDD2 reaching UVLO+ (2.18 V), with no handshake or clock training. SI86SO21BC-ASR achieves this through self-synchronizing modulation and integrated reset circuitry on both sides.
How does the default-low fail-safe mode function in SI86SO21BC-ASR during power loss?
When VDD1 drops below UVLO– (2.05 V), SI86SO21BC-ASR forces A1/A2 inputs and B1/B2 outputs low via internal 100 kΩ pulldowns. This ensures gate drivers disable and BMS monitoring halts safely. SI86SO21BC-ASR maintains this state until VDD1 exceeds RSTB+ (~1.7 V), then reloads its default-low configuration.
What is the maximum data rate supported by SI86SO21BC-ASR and what timing parameters enable high-speed operation?
SI86SO21BC-ASR supports up to 150 Mbps with 9 ns typical propagation delay, 4.5 ns max pulse width distortion, and 3 ns max channel-to-channel skew. These values are guaranteed across –40 to +125 °C and 2.25–5.5 V supply range. SI86SO21BC-ASR achieves this using RF carrier modulation instead of pulse-based schemes, reducing jitter to 350 ps peak eye diagram jitter.
Can SI86SO21BC-ASR operate with mismatched supply voltages on Side A and Side B?
Yes-SI86SO21BC-ASR supports independent 2.25–5.5 V supplies on VDD1 and VDD2, enabling 3.3 V MCU interfacing with 5 V gate drivers or ADCs. Each side has autonomous UVLO and reset detection; VDD1 can be powered while VDD2 remains off, and vice versa. SI86SO21BC-ASR maintains isolation integrity and correct logic translation across all valid combinations.
SI86SO21BC-ASR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- Si86SOx
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- General Purpose
- Isolated Power:
- Yes
- Number of Channels:
- 2
- Inputs - Side 1/Side 2:
- 1/1
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 13.5ns, 13.5ns
- Pulse Width Distortion (Max):
- 2.5ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
SI86SO21BC-ASR FAQ
1.How can I place an order for SI86SO21BC-ASR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86SO21BC-ASR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86SO21BC-ASR reliable?
The price and inventory of SI86SO21BC-ASR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86SO21BC-ASR is usually 5 days.
3.What payment methods are accepted for SI86SO21BC-ASR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86SO21BC-ASR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86SO21BC-ASR?
SI86SO21BC-ASR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86SO21BC-ASR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86SO21BC-ASR?
For technical support, including SI86SO21BC-ASR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86SO21BC-ASR requirements.
6.How does Aetrix verify that SI86SO21BC-ASR is sourced from the original manufacturer or authorized distributors?
All SI86SO21BC-ASR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86SO21BC-ASR meets industry standards.
7.What is the process for return or replacement of SI86SO21BC-ASR?
All SI86SO21BC-ASR units undergo pre-shipment inspection (PSI). If there is an issue with SI86SO21BC-ASR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86SO21BC-ASR part is unused and in its original packaging.
Return procedure for SI86SO21BC-ASR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86SO21BC-ASR Tags
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