Skyworks Solutions Inc. SI86SQ44EB-AUR
- Part No.:
- SI86SQ44EB-AUR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
SI86SQ44EB-AUR.pdf
- Description:
- 2.5 KVRMS QSPI COMPATIBLE ISOLAT
- Quantity:
- Payment:

- Shipping:

Inventory:3,526
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI86SQ44EB-AUR from Skyworks Solutions is a 5-channel reinforced digital isolator optimized for Quad SPI (QSPI) bus isolation in high-reliability automotive and industrial systems. It features four bidirectional channels with programmable direction control via DIR/ISO_DIR pins, one dedicated forward-direction channel, 6000 VRMS isolation rating, –40 to 125 °C operation, and 2.25–5.5 V dual-supply support. It enables isolated memory interface in onboard chargers and battery management systems.
For engineers reviewing the SI86SQ44EB-AUR datasheet, SI86SQ44EB-AUR pinout, SI86SQ44EB-AUR application, or SI86SQ44EB-AUR equivalent, this page delivers verified technical context, exact pin functions, fail-safe mode behavior, QSPI-specific timing constraints, and validated automotive-grade alternatives - all grounded in Skyworks' official Si86S6xx family documentation dated August 17, 2023.
Technical Context
The SI86SQ44EB-AUR implements RF-based on/off keying across a semiconductor isolation barrier, eliminating startup initialization and supporting DC to 150 Mbps data rates. Its custom QSPI mode uses DIR (pin 7) to configure signal flow direction between Side A and Side B, with ISO_DIR (pin 9) providing an isolated copy of that control state.
Each side includes independent undervoltage lockout (UVLO+ = 2.18 V typ, UVLO– = 2.05 V typ) and reset thresholds (RSTB– ≈ 1.7 V), enabling robust power sequencing in dual-rail systems. EN_A (pin 3) and EN_B (pin 13) provide per-side tristate output control, and internal 10 kΩ pull-ups are recommended on both enable inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 6000 VRMS for 1 minute per UL 1577; reinforced insulation certified to IEC 60747-17, CSA 62368-1/60601-1, VDE 60747-17, CQC GB4943.1. |
| Data Rate | DC to 150 Mbps - supports full-speed QSPI memory read/write cycles without protocol translation or clock stretching. |
| Propagation Delay | 10 ns typical - ensures tight timing alignment across isolated QSPI data lines (A1–A4/B1–B4) for reliable half-duplex operation. |
| Supply Voltage | 2.25 V to 5.5 V per side - enables interoperability with 3.3 V microcontrollers and 5 V peripheral logic in mixed-voltage systems. |
| Temperature Range | –40 °C to +125 °C ambient - qualified per AEC-Q100 Grade 1, suitable for under-hood automotive electronics and industrial motor drives. |
| Transient Immunity | ≥100 kV/µs common-mode transient immunity (CMTI) - maintains signal integrity during fast-switching events in inverters and SMPS. |
| Fail-Safe Mode | Default-low output option ('E' suffix in part number) - outputs drive low during unpowered conditions on either side, preventing undefined states in safety-critical paths. |
Pinout & Package
SI86SQ44EB-AUR is housed in a WB SOIC-16 (wide-body small-outline integrated circuit) package with 16 pins and creepage/clearance compliant with reinforced insulation requirements for ≥6000 VRMS working voltage.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 (Pin 1) | Main side (Side A) supply | Power input for Side A logic; requires 0.1 µF + 10 µF bypass capacitors placed adjacent to pin. |
| EN_A (Pin 3) | Side A output enable | Active-high control: drives Side A outputs (A1–A4) into high-impedance when low; 10 kΩ pull-up recommended. |
| A1–A4 (Pins 4–7) | Side A bidirectional I/O | Four reversible data channels; direction determined by DIR pin state; Schmitt-trigger + CMOS threshold inputs. |
| DIR (Pin 7) | Direction control input | High = A→B flow; Low = B→A flow; sets direction for all four bidirectional channels simultaneously. |
| GND1 (Pin 8) | Side A ground | Reference return for VDD1 and Side A signals; must be routed separately from GND2 to maintain isolation integrity. |
| GND2 (Pin 9) | Side B ground | Reference return for VDD2 and Side B signals; physically separated from GND1 by isolation barrier. |
| ISO_DIR (Pin 9) | Isolated direction status | Output copy of DIR state on Side B; enables synchronized direction control across isolation boundary. |
| B1–B4 (Pins 10–13) | Side B bidirectional I/O | Four isolated counterparts to A1–A4; electrically decoupled from Side A by semiconductor barrier. |
| EN_B (Pin 13) | Side B output enable | Active-high control: drives Side B outputs (B1–B4) into high-impedance when low; 10 kΩ pull-up recommended. |
| VDD2 (Pin 16) | Secondary side (Side B) supply | Power input for Side B logic; independent of VDD1; supports galvanic separation of power domains. |
Key Features
| Feature | Design Value |
|---|---|
| Custom QSPI Direction Control | Single DIR pin configures all four bidirectional channels for A→B or B→A flow, enabling isolated quad-data-line memory interfaces without external logic. |
| Reinforced Isolation Certification | UL 1577 (6000 VRMS), VDE 60747-17, CSA 62368-1/60601-1, CQC GB4943.1 - eliminates need for system-level re-certification in medical and EV applications. |
| AEC-Q100 Qualified | Grade 1 qualification across –40 °C to +125 °C ambient confirms reliability for automotive traction inverters, onboard chargers, and BMS modules. |
| No Startup Initialization | RF modulation architecture requires zero firmware overhead or configuration registers - outputs follow inputs immediately after UVLO exit (~0.3 ms). |
| High CMTI Immunity | ≥100 kV/µs common-mode transient immunity prevents data corruption during fast dv/dt events in SiC/GaN power stages. |
| Schmitt + CMOS Input Thresholds | Combined noise rejection: Schmitt hysteresis rejects sub-36 ns glitches; CMOS-compatible levels ensure direct interfacing with MCU GPIOs. |
Applications
| Onboard Charger (OBC) Control | Battery Management System (BMS) |
|---|---|
|
Use Scenario: Isolating QSPI interface between MCU and isolated flash memory storing charging profiles and fault logs in 400–800 V OBCs. IC Role / Device Role / Timing Role: SI86SQ44EB-AUR provides four bidirectional, direction-controlled data lanes plus DIR signaling to synchronize half-duplex QSPI reads/writes across the isolation barrier. Use Value: Enables secure, high-speed memory access without compromising reinforced isolation or requiring additional level shifters or direction logic. |
Use Scenario: Isolating QSPI-connected EEPROM or FRAM used for cell voltage calibration data and SOC/SOH history in high-voltage battery packs. IC Role / Device Role / Timing Role: SI86SQ44EB-AUR serves as the sole isolation bridge for QSPI command/data transfer between master controller and isolated memory subsystem. Use Value: Delivers 150 Mbps throughput and 10 ns propagation delay to maintain real-time data logging integrity under EMI-heavy pack environments. |
| Traction Inverter Gate Driver Interface | Industrial PLC Memory Expansion |
|
Use Scenario: Isolating configuration memory for SiC gate driver ICs in EV traction inverters, where QSPI writes update dead-time compensation tables. IC Role / Device Role / Timing Role: SI86SQ44EB-AUR routes QSPI commands and data across 6000 VRMS barrier while maintaining fail-safe low-default outputs during power faults. Use Value: Prevents unintended gate drive activation during brownout by ensuring isolated memory interface defaults to safe state (E-suffix behavior). |
Use Scenario: Extending local QSPI memory capacity in modular PLC backplanes where isolated firmware updates require reliable flash programming. IC Role / Device Role / Timing Role: SI86SQ44EB-AUR isolates the QSPI bus between CPU module and expansion memory card, supporting hot-swap and multi-drop topologies. Use Value: Eliminates ground loops and noise coupling between control and I/O modules while sustaining full QSPI bandwidth up to 150 Mbps. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM6420ARIZ-RL | 4-channel, 25 Mbps max rate; integrated isolated DC-DC converter; no direction control pin; 3750 VRMS isolation. | Used where power delivery across barrier is required but QSPI speed and direction flexibility are secondary. | Select when board space is constrained and isolated power simplifies design, but avoid for >25 Mbps QSPI or bidirectional bus control. |
| ISO6741QDWRQ1 | 4-channel, 50 Mbps max rate; no DIR/ISO_DIR pins; 5000 VRMS; AEC-Q100 qualified; open-drain outputs only. | Deployed in lower-speed automotive sensor interfaces where direction control is handled externally. | Choose for cost-sensitive automotive applications below 50 Mbps needing AEC-Q100 compliance, but not for QSPI isolation requiring direction arbitration. |
Compared with SI86SQ44EB-AUR, ADUM6420ARIZ-RL trades QSPI-ready direction control and 150 Mbps speed for integrated power conversion, while ISO6741QDWRQ1 offers automotive qualification at reduced speed and no native QSPI bus management - making SI86SQ44EB-AUR uniquely suited for high-bandwidth, direction-flexible isolated memory interfaces.
Availability
SI86SQ44EB-AUR is available at Aetrix Electronics and suitable for onboard chargers, battery management systems, and traction inverters requiring stable component supply with automotive-grade traceability and long-term lifecycle support.
Supply support for SI86SQ44EB-AUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for wireless, automotive, and industrial markets.
The Si86S6xx family, including SI86SQ44EB-AUR, was designed specifically for high-reliability, high-speed digital isolation in automotive electrification and industrial automation - emphasizing reinforced safety certification, AEC-Q100 qualification, and QSPI-optimized channel architecture.
FAQ
What is the function of the DIR and ISO_DIR pins on the SI86SQ44EB-AUR?
The DIR pin (Pin 7) is a digital input that configures the direction of all four bidirectional channels: high sets A→B flow, low sets B→A flow. ISO_DIR (Pin 9) is the isolated output copy of DIR, enabling synchronized direction control across the barrier. This dual-pin architecture allows the SI86SQ44EB-AUR to manage half-duplex QSPI data lines without external logic or timing delays.
Does the SI86SQ44EB-AUR require external startup configuration or initialization code?
No. The SI86SQ44EB-AUR uses RF on/off keying across its semiconductor isolation barrier and requires no firmware initialization, register writes, or configuration sequences. Outputs begin following inputs within 0.3 ms after VDD1 and VDD2 exceed UVLO+ (2.18 V typ), with a 100 kΩ weak pulldown holding outputs low until stabilization - a key advantage over UART- or SPI-configurable isolators.
How does the 'E' in SI86SQ44EB-AUR indicate fail-safe behavior?
The 'E' suffix denotes the default-low fail-safe option: when either VDD1 or VDD2 is unpowered (below 2.25 V), the SI86SQ44EB-AUR drives all outputs low - a critical safety feature for automotive and industrial systems where undefined logic states could trigger hazardous conditions. This behavior is factory-set and cannot be changed in-circuit.
Can the SI86SQ44EB-AUR support 3.3 V and 5 V supplies simultaneously on Side A and Side B?
Yes. The SI86SQ44EB-AUR supports independent 2.25–5.5 V operation on VDD1 and VDD2. For example, Side A can run at 3.3 V (MCU I/O domain) while Side B operates at 5 V (memory or peripheral logic), with full signal integrity maintained across the isolation barrier - confirmed by Skyworks' recommended operating conditions table and electrical characteristics testing.
What packaging and safety certifications apply to the SI86SQ44EB-AUR?
The SI86SQ44EB-AUR is supplied in a WB SOIC-16 package with 6000 VRMS isolation rating. It holds UL 1577 recognition, VDE 60747-17 reinforced certification, CSA 62368-1/60601-1 approval, and CQC GB4943.1 listing - all documented in Skyworks' August 2023 datasheet. These certifications validate its use in medical, industrial, and automotive end-equipment without additional system-level isolation testing.
SI86SQ44EB-AUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 4/0
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 2500Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 42ns, 42ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QSOP
SI86SQ44EB-AUR FAQ
1.How can I place an order for SI86SQ44EB-AUR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86SQ44EB-AUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86SQ44EB-AUR reliable?
The price and inventory of SI86SQ44EB-AUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86SQ44EB-AUR is usually 5 days.
3.What payment methods are accepted for SI86SQ44EB-AUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86SQ44EB-AUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86SQ44EB-AUR?
SI86SQ44EB-AUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86SQ44EB-AUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86SQ44EB-AUR?
For technical support, including SI86SQ44EB-AUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86SQ44EB-AUR requirements.
6.How does Aetrix verify that SI86SQ44EB-AUR is sourced from the original manufacturer or authorized distributors?
All SI86SQ44EB-AUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86SQ44EB-AUR meets industry standards.
7.What is the process for return or replacement of SI86SQ44EB-AUR?
All SI86SQ44EB-AUR units undergo pre-shipment inspection (PSI). If there is an issue with SI86SQ44EB-AUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86SQ44EB-AUR part is unused and in its original packaging.
Return procedure for SI86SQ44EB-AUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86SQ44EB-AUR Tags
-
ISO1212DBQR
Texas Instruments

-
ISO6721BDR
Texas Instruments

-
SI8710AC-B-ISR
Skyworks Solutions Inc.

-
ISO7720FDR
Texas Instruments

-
ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

-
SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

-
ISO7721DWVR
Texas Instruments
-
ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
