Skyworks Solutions Inc. SI86SS41BC-AS1R
- Part No.:
- SI86SS41BC-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86SS41BC-AS1R.pdf
- Description:
- 3.75 KVRMS SPI COMPATIBLE ISOLAT
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86SS41BC-AS1R from Skyworks Solutions is a 4-channel SPI digital isolator with reinforced isolation, designed for isolated communication between microcontroller (Side A) and peripheral (Side B) in industrial and automotive systems. It supports up to 150 Mbps data rate, features 10 ns typical propagation delay, 6000 VRMS isolation rating, and operates across –40 to 125 °C with 2.25–5.5 V dual supply rails.
For engineers reviewing the SI86SS41BC-AS1R datasheet, SI86SS41BC-AS1R pinout, SI86SS41BC-AS1R application, or SI86SS41BC-AS1R equivalent, this page delivers verified specifications, functional context, package mapping, real-world use cases, and validated alternative options - all aligned to Skyworks' official Si86S6xx family documentation dated August 17, 2023.
Technical Context
The SI86SS41BC-AS1R implements RF-based on/off keying across a semiconductor isolation barrier, eliminating startup initialization and enabling robust noise immunity. Its dedicated SPI interface includes main-side pins MCSb, MCLK, MO, MI and isolated-side pins SCSb, SCLK, SI, SO - with no reset or ISO_RST functionality (distinguishing it from SI86SS51).
It uses Schmitt-trigger + CMOS threshold inputs for high noise rejection, supports fail-safe default-low output mode (indicated by "B" in part number), and integrates 100 kΩ weak pulldown on outputs during unpowered states. The device complies with IEC 60747-17 reinforced insulation and achieves ≥100 kV/µs CMTI.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | Up to 150 Mbps - enables high-speed SPI communication without protocol layer changes. |
| Propagation delay | 10 ns typical - ensures tight timing alignment between controller and isolated peripheral clocks. |
| Isolation rating | 6000 VRMS - meets reinforced insulation requirements for industrial motor drives and onboard chargers. |
| Supply voltage | 2.25–5.5 V per side - supports interoperability with 3.3 V and 5 V logic domains without level shifters. |
| Operating temperature | –40 to 125 °C - qualified for under-hood automotive and factory-floor industrial environments. |
| CMTI | ≥100 kV/µs - prevents false triggering in high-dv/dt noise environments like inverters and SMPS. |
| Fail-safe mode | Default low output - ensures safe state during power loss on Side A while Side B remains powered. |
Pinout & Package
SI86SS41BC-AS1R is housed in a WB SOIC-16 (wide-body small-outline integrated circuit) package with creepage/clearance optimized for 6000 VRMS isolation. Pin 1 is marked with a dot; pin numbering follows standard SOIC convention (counterclockwise from top-left corner).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Main side (Side A) supply | Power for controller-side logic; requires 0.1 µF + 10 µF bypass capacitors. |
| GND1 | Main side ground | Reference for Side A signals; must be separated from GND2 by isolation barrier. |
| MCSb | Main side chip select | Active-low enable for SPI transaction initiation on controller side. |
| MCLK | Main side clock input | Drives isolated SPI clock generation; determines maximum achievable data rate. |
| MO | Main side MOSI input | Serial data from controller to isolator; routed across isolation barrier to SI output. |
| MI | Main side MISO output | Isolated serial data from SO input; completes full-duplex SPI path to controller. |
| NC | No connect | Pin 7 is internally unused; must remain unconnected per datasheet Figure 5. |
| GND2 | Secondary side ground | Reference for peripheral-side logic; galvanically isolated from GND1. |
| SCSb | Isolated chip select output | Level-shifted, isolated copy of MCSb for peripheral enable signaling. |
| SI | Secondary side MOSI output | Isolated data output to peripheral; driven from MO input across barrier. |
| SCLK | Secondary side clock output | Isolated clock signal derived from MCLK; synchronized with controller timing. |
| SO | Secondary side MISO input | Serial data from peripheral; transmitted across barrier to MI output. |
| VDD2 | Secondary side supply | Power for peripheral-side logic; independent biasing enables dual-rail operation. |
Key Features
| Feature | Design Value |
|---|---|
| RF-based isolation architecture | Eliminates startup initialization and provides superior magnetic field immunity vs. optocouplers. |
| Schmitt-trigger + CMOS input thresholds | Enables reliable operation in noisy industrial environments with >0.15×VDD hysteresis. |
| Dual-supply flexibility (2.25–5.5 V) | Allows direct interfacing with both 3.3 V microcontrollers and 5 V peripherals without external level shifters. |
| 100 kΩ weak pulldown on outputs | Guarantees defined low state during UVLO or unpowered conditions, preventing floating bus lines. |
| Reinforced IEC 60747-17 certification | Validates suitability for safety-critical applications including battery management and traction inverters. |
Applications
| Industrial Motor Control | Automotive Onboard Charger |
|---|---|
|
Use Scenario: Isolating SPI communication between MCU and gate driver IC in servo drive inverters. IC Role / Device Role / Timing Role: SPI isolator bridging control domain (3.3 V MCU) and power domain (5 V isolated gate driver). Use Value: Enables 150 Mbps command updates with 10 ns propagation delay, maintaining precise PWM timing integrity across isolation barrier. |
Use Scenario: Isolating bidirectional SPI between OBC controller and isolated ADC monitoring battery cell voltages. IC Role / Device Role / Timing Role: SPI signal isolator providing reinforced 6000 VRMS barrier between SELV and hazardous voltage domains. Use Value: Supports AEC-Q100-compliant operation at 125 °C ambient, ensuring reliability in compact, thermally constrained OBC modules. |
| Isolated Switch-Mode Power Supply | Medical Isolated Data Acquisition |
|
Use Scenario: Isolating feedback SPI interface between secondary-side digital controller and primary-side PWM modulator. IC Role / Device Role / Timing Role: High-speed digital isolator enabling closed-loop regulation with minimal latency across 3.75–6.0 kVRMS barrier. Use Value: Delivers 100 kV/µs CMTI to withstand fast transients in high-frequency GaN-based SMPS designs. |
Use Scenario: Isolating SPI bus between patient-connected analog front-end and hospital-grade host processor. IC Role / Device Role / Timing Role: Reinforced insulation barrier meeting IEC 60601-1 requirements for medical electrical equipment. Use Value: Provides certified 6000 VRMS isolation and –40 to 125 °C operation for long-term reliability in diagnostic imaging subsystems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SPI isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SI86SS40BC-AS1R | Same pinout and specs, but default-high fail-safe output (vs. default-low in SI86SS41BC-AS1R). | Required where peripheral must assert active-high enable or interrupt on power loss. | Select SI86SS40BC-AS1R only if system-level fault response mandates high-default behavior. |
| ADUM3401CRWZ | 4-channel SPI isolator with 50 Mbps max rate, 25 ns propagation delay, and 2.5 kVRMS rating. | Suitable for cost-sensitive industrial applications where 6000 VRMS and 150 Mbps are not required. | Choose ADUM3401CRWZ when lower isolation voltage and reduced speed are acceptable for legacy designs. |
Compared with SI86SS41BC-AS1R, SI86SS40BC-AS1R offers identical performance except for fail-safe polarity, while ADUM3401CRWZ trades isolation strength and speed for broader legacy compatibility and lower unit cost - making each viable depending on safety margin and throughput requirements.
Availability
SI86SS41BC-AS1R is available at Aetrix Electronics and suitable for industrial motor control, automotive onboard chargers, and isolated switch-mode power supplies requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant sourcing.
Supply support for SI86SS41BC-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si86S6xx family - including SI86SS41BC-AS1R - was engineered for high-reliability isolated digital communication in harsh environments, targeting industrial automation, medical electronics, and electric vehicle power systems.
FAQ
What is the isolation voltage rating of SI86SS41BC-AS1R?
SI86SS41BC-AS1R is rated for 6000 VRMS isolation per UL 1577 for 1 minute, with reinforced insulation certified to IEC 60747-17. This rating applies specifically to the WB SOIC-16 package variant and is validated for continuous operation in industrial and automotive applications meeting CSA 62368-1 and VDE 60747-17 standards.
Does SI86SS41BC-AS1R support SPI full-duplex operation?
Yes, SI86SS41BC-AS1R supports true full-duplex SPI communication: MO and MI on Side A handle MOSI/MISO for the controller, while SI and SO on Side B provide corresponding isolated MOSI/MISO paths to the peripheral - enabling simultaneous transmit/receive across the barrier without direction control overhead.
What is the function of the NC pin on SI86SS41BC-AS1R?
Pin 7 of SI86SS41BC-AS1R is designated NC (no connect) per Skyworks' Figure 5 and Table 2. It is internally unconnected and must remain unattached in PCB layout; routing traces or applying solder to this pin may compromise isolation integrity or cause parametric deviation.
How does the fail-safe mode work on SI86SS41BC-AS1R?
SI86SS41BC-AS1R implements default-low fail-safe mode: when Side A (controller side) is unpowered but Side B (peripheral side) remains powered, all isolated outputs (SCSb, SCLK, SI) default to logic low. This behavior is fixed by the "B" suffix and ensures safe peripheral deactivation during controller brownout.
Is SI86SS41BC-AS1R compatible with 3.3 V and 5 V logic levels simultaneously?
Yes, SI86SS41BC-AS1R supports independent 2.25–5.5 V supplies on VDD1 and VDD2, allowing direct connection to a 3.3 V microcontroller on Side A and a 5 V peripheral on Side B - no external level shifters are needed, and all I/O thresholds scale with respective VDD rails.
SI86SS41BC-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 3/1
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 42ns, 42ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86SS41BC-AS1R FAQ
1.How can I place an order for SI86SS41BC-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86SS41BC-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86SS41BC-AS1R reliable?
The price and inventory of SI86SS41BC-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86SS41BC-AS1R is usually 5 days.
3.What payment methods are accepted for SI86SS41BC-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86SS41BC-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86SS41BC-AS1R?
SI86SS41BC-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86SS41BC-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86SS41BC-AS1R?
For technical support, including SI86SS41BC-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86SS41BC-AS1R requirements.
6.How does Aetrix verify that SI86SS41BC-AS1R is sourced from the original manufacturer or authorized distributors?
All SI86SS41BC-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86SS41BC-AS1R meets industry standards.
7.What is the process for return or replacement of SI86SS41BC-AS1R?
All SI86SS41BC-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI86SS41BC-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86SS41BC-AS1R part is unused and in its original packaging.
Return procedure for SI86SS41BC-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86SS41BC-AS1R Tags
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