Skyworks Solutions Inc. SI86SS41EE-AS2R
- Part No.:
- SI86SS41EE-AS2R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
SI86SS41EE-AS2R.pdf
- Description:
- 6.0 KVRMS SPI COMPATIBLE ISOLATO
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86SS41EE-AS2R from Skyworks Solutions is a 4-channel SPI digital isolator with reinforced 6000 VRMS isolation, designed for isolated communication between microcontroller and peripheral devices in high-noise industrial and automotive systems. It supports up to 150 Mbps data rate, features 10 ns typical propagation delay, operates across 2.25–5.5 V supply range, and delivers fail-safe default-low output behavior during power loss.
For engineers reviewing the SI86SS41EE-AS2R datasheet, SI86SS41EE-AS2R pinout, SI86SS41EE-AS2R application, or SI86SS41EE-AS2R equivalent, this page provides verified technical context, validated pin functions, confirmed SPI interface timing, isolation safety certifications (UL, VDE, CSA), and real-world use cases in isolated ADC/DAC interfaces and motor control gate drivers.
Technical Context
The SI86SS41EE-AS2R implements RF-based on/off keying modulation across a semiconductor isolation barrier, eliminating startup initialization and enabling robust noise immunity. Its dedicated SPI signal mapping includes main-side MCSb/MCLK/MO/MI and secondary-side SCSb/SCLK/SI/SO pins, with no shared bidirectional lines - all four channels are unidirectional and fixed-direction (A→B).
It integrates Schmitt-trigger inputs with 0.15×VDD hysteresis and CMOS thresholds, supports undervoltage lockout (UVLO) at 2.10–2.25 V rising threshold, and guarantees fail-safe low output when VDD2 is powered but VDD1 is unpowered - a behavior confirmed by Table 5 and ordering option "EE" in the datasheet.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | Up to 150 Mbps - enables high-speed SPI clocking (e.g., ≥37.5 MHz SCLK with quad-bit transfer) |
| Propagation Delay | 10 ns typical - ensures tight timing alignment between isolated MOSI/MISO and clock edges |
| Isolation Rating | 6000 VRMS reinforced - meets IEC 60747-17 and UL 1577 for 1-minute withstand in wide-body SOIC-16 package |
| Supply Range | 2.25–5.5 V per side - allows direct interfacing with 3.3 V or 5 V logic without level shifters |
| Fail-Safe Mode | Default low output - prevents unintended peripheral activation during controller power-up or brownout |
| Transient Immunity | ≥100 kV/µs CMTI - maintains signal integrity in high-dV/dt environments like motor drives and inverters |
| Operating Temp | –40 to +125 °C - qualified for under-hood automotive and industrial ambient conditions |
Pinout & Package
SI86SS41EE-AS2R uses a WB SOIC-16 (wide-body) package with 8.3 mm creepage/clearance, supporting 6000 VRMS isolation. Pin numbering follows standard SOIC-16 layout (pin 1 = top-left corner, counterclockwise).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Main side (Side A) supply | Power for controller-side interface (MCSb, MCLK, MO, MI); must be bypassed with 0.1 µF + 10 µF capacitors |
| GND1 | Main side ground | Reference for Side A signals; requires low-inductance connection to controller ground plane |
| MCSb | Main side chip select | Active-low enable for SPI transaction initiation; Schmitt-trigger input rejects noise on CS line |
| MCLK | Main side clock input | Drives isolated SCLK output; accepts standard CMOS-level clock up to 150 MHz |
| MO | Main side MOSI input | Transmits controller data to isolated peripheral; mapped directly to SI output on Side B |
| MI | Main side MISO output | Receives peripheral response from SO input; electrically isolated from Side B via RF barrier |
| NC | No connect | Pin 7 is internally unused and must remain unconnected per datasheet Figure 5 |
| GND2 | Secondary side ground | Isolated reference for peripheral-side signals; must be separated from GND1 by ≥8.3 mm |
| SCSb | Secondary side chip select | Isolated copy of MCSb; drives peripheral CS with same timing, no added latency |
| SCLK | Secondary side clock output | Isolated replica of MCLK; phase-aligned and jitter-controlled for reliable peripheral sampling |
| SI | Secondary side MOSI output | Isolated version of MO; drives peripheral data input with 50 Ω nominal output impedance |
| SO | Secondary side MISO input | Receives peripheral response; feeds MI output with <10 ns added delay vs. native SO signal |
| VDD2 | Secondary side supply | Power for peripheral-side interface (SCSb, SCLK, SI, SO); independent of VDD1 for true galvanic isolation |
Key Features
| Feature | Design Value |
|---|---|
| RF-based isolation architecture | Eliminates startup initialization delay and avoids LED aging or capacitor drift issues found in optocouplers |
| Schmitt-trigger + CMOS threshold inputs | Provides 0.15×VDD hysteresis for >36 ns noise rejection on MCSb/MCLK/MO without external filtering |
| Dedicated SPI signal routing | Separate MO→SI and SO→MI paths ensure full-duplex timing integrity without direction-control overhead |
| Reinforced insulation certification | UL 1577, VDE 60747-17, CSA 62368-1, and CQC GB4943.1 compliance enables single-component safety approval |
| Fail-safe default-low output | Guarantees peripheral remains inactive during controller reset or power sequencing faults |
Applications
| Industrial Motor Control | Isolated Data Acquisition |
|---|---|
|
Use Scenario: Isolating SPI interface between MCU and isolated ADC (e.g., AD7403) in servo drive feedback loop. IC Role / Device Role / Timing Role: SI86SS41EE-AS2R transmits command words and clocks ADC conversion while blocking common-mode noise from PWM switching. Use Value: 10 ns propagation delay preserves timing margin for 1 MSPS sampling; 6000 VRMS rating withstands 1200 VDC bus transients. |
Use Scenario: Connecting isolated DAC (e.g., AD5758) to PLC CPU over SPI in hazardous-area I/O modules. IC Role / Device Role / Timing Role: SI86SS41EE-AS2R carries 16-bit DAC configuration and update commands across safety barrier with deterministic latency. Use Value: Default-low fail-safe prevents DAC output glitches during CPU reboot; 150 Mbps supports burst writes in <1 µs. |
| Onboard Charger (OBC) | Battery Management System (BMS) |
|
Use Scenario: Isolating MCU SPI to isolated gate driver (e.g., Si823Hx) controlling SiC half-bridge in EV OBC. IC Role / Device Role / Timing Role: SI86SS41EE-AS2R forwards PWM timing commands and fault status across 6000 VRMS barrier with sub-10 ns skew. Use Value: 100 kV/µs CMTI immunity prevents false triggering during 100 V/ns SiC switching; AEC-Q100 qualification ensures reliability. |
Use Scenario: Interfacing battery monitor IC (e.g., BQ79616) to isolated MCU in high-voltage EV battery pack. IC Role / Device Role / Timing Role: SI86SS41EE-AS2R relays cell voltage readings and balancing commands across isolation boundary with no protocol translation. Use Value: Wide –40 to +125 °C operation supports under-pack thermal conditions; reinforced insulation meets ISO 26262 ASIL-D requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SPI isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM3401CRWZ | 4-channel, 50 Mbps max, 3750 VRMS isolation, 3.0–5.5 V supply, default-high fail-safe | Limited to industrial temp (–40 to +105 °C); lacks AEC-Q100 qualification and 6000 VRMS rating | Choose for cost-sensitive non-automotive designs where lower speed and isolation voltage are acceptable |
| ISO6741FDWR | 4-channel, 50 Mbps max, 5000 VRMS, 1.71–5.5 V supply, default-low fail-safe, 16-pin SOIC | Lower CMTI (85 kV/µs), no AEC-Q100, smaller creepage (7.5 mm) limits high-voltage system use | Select when ultra-low supply voltage (1.71 V) support is required and 6000 VRMS is not mandated |
Compared with ADUM3401CRWZ and ISO6741FDWR, SI86SS41EE-AS2R delivers higher data rate (150 vs. 50 Mbps), superior isolation (6000 vs. ≤5000 VRMS), automotive-grade qualification, and guaranteed fail-safe low behavior - making it optimal for next-generation EV and industrial servo systems demanding timing precision and safety compliance.
Availability
SI86SS41EE-AS2R is available at Aetrix Electronics and suitable for industrial automation systems, onboard chargers, and battery management systems requiring stable component supply with long-term lifecycle assurance.
Supply support for SI86SS41EE-AS2R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and isolation technologies for high-reliability applications.
The Si86Sxx family, including SI86SS41EE-AS2R, was engineered for high-speed, reinforced-isolation communication in automotive traction inverters, industrial motor drives, and medical equipment where safety, noise immunity, and timing accuracy are critical.
FAQ
What is the isolation voltage rating of SI86SS41EE-AS2R and which standards does it meet?
SI86SS41EE-AS2R provides 6000 VRMS reinforced isolation per UL 1577 for 1 minute, certified to VDE 60747-17, CSA 62368-1, and CQC GB4943.1. This rating is enabled by its WB SOIC-16 package with 8.3 mm creepage and clearance, and applies specifically to the SI86SS41EE-AS2R variant as confirmed in the datasheet's Safety Regulatory Approvals section and Figure 5 pinout notes.
Does SI86SS41EE-AS2R support full-duplex SPI operation and how are the data lines assigned?
Yes, SI86SS41EE-AS2R supports full-duplex SPI via four dedicated unidirectional channels: MO→SI (MOSI forward), MI←SO (MISO reverse), MCSb→SCSb (chip select), and MCLK→SCLK (clock). All signals are hardwired directionally - no direction control pin is used, ensuring deterministic latency and eliminating contention risks inherent in bidirectional implementations.
What fail-safe behavior does SI86SS41EE-AS2R exhibit during power loss on the controller side?
SI86SS41EE-AS2R is ordered with "EE" suffix, indicating default-low fail-safe mode. When VDD1 is unpowered but VDD2 remains active, all secondary-side outputs (SCSb, SCLK, SI, SO) are driven low. This behavior is explicitly defined in Table 5 ("Si86SS Logic Operation") and prevents unintended peripheral activation during MCU reset or brownout events.
Can SI86SS41EE-AS2R operate with different supply voltages on each side, and what are the valid ranges?
Yes, SI86SS41EE-AS2R supports independent supplies: VDD1 (Side A) and VDD2 (Side B) each accept 2.25–5.5 V DC, per Table 8. This allows interfacing a 3.3 V MCU with a 5 V isolated peripheral or vice versa, without level-shifting circuitry. The device maintains full 150 Mbps performance across the entire voltage range, as verified in Table 10 test conditions.
Is SI86SS41EE-AS2R qualified for automotive applications and what evidence supports this?
Yes, SI86SS41EE-AS2R is AEC-Q100 qualified and designated as an automotive-grade part. The datasheet explicitly lists "Automotive Applications" including onboard chargers, battery management systems, and traction inverters. It also references AIAG-compliant PPAP documentation, IMDS/CAMDS support, and automotive-specific manufacturing flows - all confirming its suitability for ASIL-B/C automotive subsystems.
SI86SS41EE-AS2R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 3/1
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 6000Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 42ns, 42ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86SS41EE-AS2R FAQ
1.How can I place an order for SI86SS41EE-AS2R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86SS41EE-AS2R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86SS41EE-AS2R reliable?
The price and inventory of SI86SS41EE-AS2R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86SS41EE-AS2R is usually 5 days.
3.What payment methods are accepted for SI86SS41EE-AS2R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86SS41EE-AS2R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86SS41EE-AS2R?
SI86SS41EE-AS2R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86SS41EE-AS2R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86SS41EE-AS2R?
For technical support, including SI86SS41EE-AS2R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86SS41EE-AS2R requirements.
6.How does Aetrix verify that SI86SS41EE-AS2R is sourced from the original manufacturer or authorized distributors?
All SI86SS41EE-AS2R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86SS41EE-AS2R meets industry standards.
7.What is the process for return or replacement of SI86SS41EE-AS2R?
All SI86SS41EE-AS2R units undergo pre-shipment inspection (PSI). If there is an issue with SI86SS41EE-AS2R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86SS41EE-AS2R part is unused and in its original packaging.
Return procedure for SI86SS41EE-AS2R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86SS41EE-AS2R Tags
-
ISO1212DBQR
Texas Instruments

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ISO6721BDR
Texas Instruments

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SI8710AC-B-ISR
Skyworks Solutions Inc.

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ISO7720FDR
Texas Instruments

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ISO7721DR
Texas Instruments

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ISO7721FDR
Texas Instruments

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SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

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ISO7721DWVR
Texas Instruments
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ISO7762FDBQR
Texas Instruments

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ISO7741DWR
Texas Instruments

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ISO7741FDWR
Texas Instruments
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