Microchip Technology SIO1028I-JZX
- Part No.:
- SIO1028I-JZX
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
SIO1028I-JZX.pdf
- Description:
- IC INTFACE SPECIALIZED 64STQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SIO1028I-JZX from Microchip Technology is a 3.3V LPC Super I/O controller with 5V-tolerant I/O, PC99/PC01 and ACPI 1.0 compliance, supporting 19.2–33 MHz LPC bus frequencies, three NS16C550A-compatible UARTs (including one with IrDA v1.2 infrared support), and 24 GPIO pins. It serves as the primary legacy I/O hub in space-constrained notebook and embedded x86 designs requiring serial, IR, LED, and watchdog functionality.
For engineers reviewing the SIO1028I-JZX datasheet, SIO1028I-JZX pinout, SIO1028I-JZX application, or SIO1028I-JZX equivalent, key selection criteria include LPC interface timing, UART FIFO depth (16-byte), IrDA v1.2 PHY integration, GPIO count, and QFN-64 package thermal and routing constraints.
Technical Context
The SIO1028I-JZX integrates an LPC bus interface with Serial IRQ and CLKRUN# support, enabling direct connection to x86 southbridge chipsets without translation logic. Its internal architecture separates UART control, infrared transceiver logic (IRTX2/IRRX2), and ACPI-compliant power management blocks-including PME and SMI generation-into isolated register domains.
All three UARTs implement full 16C550A register sets with programmable baud rate generators, modem control signals (nRTS/nCTS/nDTR/nDSR/nDCD/nRI), and independent 16-byte TX/RX FIFOs. The second UART includes dedicated IRMODE#, IRRX3#, and IRTX2# pins for hardware-managed IrDA v1.2 Fast IR (4 Mbps) and Consumer IR protocols.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LPC Bus Frequency | 19.2–33 MHz - defines maximum host-to-SIO transaction throughput and timing margin for chipset compatibility. |
| UART Count & Type | Three NS16C550A-compatible UARTs - enables concurrent RS-232, debug console, and infrared communication without external controllers. |
| FIFO Depth | 16-byte TX/RX per UART - reduces CPU interrupt load and supports burst data transfers at up to 460 kbps. |
| Infrared Support | IrDA v1.2 (4 Mbps), HPSIR, ASKIR, Consumer IR - eliminates need for discrete IR PHY ICs in notebook docking or remote-control interfaces. |
| GPIO Pins | 24 general-purpose I/O - provides flexible board-level control of LEDs, buttons, sensors, or power sequencing logic. |
| Package | 64-pin QFN, 9 × 9 mm, 0.5 mm pitch - RoHS-compliant surface-mount package optimized for high-density laptop motherboard layouts. |
| Supply Voltage | 3.3 V operation with 5 V-tolerant I/O - allows direct interfacing with legacy 5 V peripherals while minimizing system power rail complexity. |
Pinout & Package
64-pin QFN package (9 × 9 mm body, 0.5 mm pitch), RoHS compliant, with exposed thermal pad for enhanced heat dissipation in thermally constrained notebook applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LAD0–LAD3 | LPC Address/Data Bus | Time-multiplexed bidirectional signals carrying LPC configuration and data cycles; require controlled-impedance routing. |
| LFRAME# | LPC Frame Strobe | Indicates start/end of LPC cycle; active-low, synchronized to LCLK; critical for timing setup/hold validation. |
| LDRQ# | LPC DMA Request | Open-drain signal used by SIO1028I-JZX to request DMA service from host; pulled up externally. |
| TXD2*, IRTX2* | Infrared Transmit Output | Dual-function pin: UART2 transmit or IrDA carrier-modulated output; selected via configuration register. |
| IRRX2*, IRRX3* | Infrared Receive Input | Dual-function pin: UART2 receive or IrDA demodulated input; supports both Fast IR and Consumer IR modes. |
| LED1*, LED2* | LED Driver Outputs | Open-drain outputs with programmable blink rate and polarity; drive standard 20 mA LEDs directly. |
| WDT* | Watchdog Timer Output | Active-low reset or NMI assertion pin; configurable as reset pulse or continuous output for external monitoring. |
| GP[11:13]*, GP[20:23]*, etc. | General Purpose I/O | 24 multifunction pins configurable as input, output, or alternate function (e.g., wake-up event sources). |
Key Features
| Feature | Design Value |
|---|---|
| ACPI 1.0 Compliance | Enables OS-directed power management including S3/S4 sleep states, PME wake events, and SMI-based firmware hooks. |
| Three Independent UARTs | Eliminates need for external UART expanders in designs requiring simultaneous serial console, modem, and IR communication paths. |
| Integrated IrDA v1.2 PHY | Reduces BOM count and PCB area by embedding 4 Mbps infrared encoding/decoding logic, avoiding discrete transceivers like TFDS4000. |
| Programmable LED Drivers | Two dedicated open-drain outputs with software-configurable blink intervals simplify status indicator implementation without external timers. |
| Watchdog Timer with Output Pin | Hardware reset supervision with optional WDT* pin assertion ensures deterministic recovery from firmware hangs in unattended systems. |
Applications
| Notebook System Management | Industrial Thin Client |
|---|---|
Use Scenario: Embedded controller in ultra-thin notebook platforms managing keyboard, touchpad, battery charging, and thermal sensors via GPIO and SMBus. IC Role / Device Role / Timing Role: Primary LPC-connected Super I/O providing UART-based debug console, ACPI-compliant power sequencing, and wake-on-LAN/keyboard events. Use Value: Consolidates legacy I/O functions into single 9×9 mm QFN, reducing motherboard layer count and enabling sub-15 mm chassis height. | Use Scenario: Fanless industrial thin client running Linux with serial diagnostics, IR remote control, and dual LED status indicators. IC Role / Device Role / Timing Role: Central I/O hub handling RS-232 console, IrDA v1.2 remote pairing, and GPIO-driven fan speed control. Use Value: 16-byte UART FIFOs sustain 460 kbps debug logging without CPU overhead; IrDA PHY eliminates external transceiver cost and layout risk. |
| Medical Point-of-Care Terminal | POS Kiosk with IR Remote |
Use Scenario: CE-certified handheld diagnostic terminal requiring ESD-hardened serial ports, low-power wake-on-serial, and LED feedback for test status. IC Role / Device Role / Timing Role: LPC I/O companion to ARM/x86 SoC, delivering AC/DC-safe UART isolation interface and configurable GPIO wakeup sources. Use Value: 5 V-tolerant I/O simplifies connection to isolated RS-232 level shifters; ACPI-compliant PME enables fast resume from deep sleep. | Use Scenario: Retail self-service kiosk using infrared remote for menu navigation and status indication via two blinking LEDs. IC Role / Device Role / Timing Role: Infrared subsystem controller with integrated IrDA v1.2 PHY and dual programmable LED drivers. Use Value: Hardware IR modulation/demodulation at 4 Mbps ensures reliable remote response under ambient light; LED blink registers eliminate MCU polling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Super I/O controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Nuvoton NCT6776D | 48-pin QFP package; supports LPC up to 33 MHz but lacks integrated IrDA PHY; requires external IR transceiver. | Targeted at desktop motherboards with larger board area; no native Fast IR support limits remote-control use cases. | Select when IrDA is not required and QFP assembly is preferred over QFN. |
| ITE IT8786E | 128-pin LQFP; includes hardware PWM fan control and temperature sensor interface not present in SIO1028I-JZX. | Used in server management controllers where thermal monitoring and multi-fan control are mandatory. | Choose for thermally complex systems needing on-die thermal sensing and fan regulation logic. |
Compared with NCT6776D and IT8786E, the SIO1028I-JZX uniquely delivers IrDA v1.2 PHY integration in a compact 64-pin QFN, making it optimal for space-constrained mobile and embedded designs requiring infrared communication without added components.
Availability
SIO1028I-JZX is available at Aetrix Electronics and suitable for notebook platform design, industrial thin client development, and medical point-of-care terminal manufacturing requiring stable component supply and long-term lifecycle support.
Supply support for SIO1028I-JZX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and interface ICs, with a focus on embedded control and connectivity solutions.
The SIO1028I-JZX belongs to Microchip's legacy Super I/O product line, designed specifically for x86-based notebook and embedded systems requiring consolidated LPC-connected serial, infrared, GPIO, and power management functions.
FAQ
What is the maximum supported LPC bus frequency for the SIO1028I-JZX?
The SIO1028I-JZX supports LPC bus frequencies from 19.2 MHz to 33 MHz, as specified in its official Microchip datasheet DS00001818A. This range ensures compatibility with Intel ICH7–ICH10 and compatible southbridges. Operation outside this window may result in unreliable configuration reads or data corruption during LPC transactions. The SIO1028I-JZX does not support 48 MHz or higher LPC speeds found in newer platforms.
Does the SIO1028I-JZX include hardware support for IrDA v1.2 Fast IR?
Yes, the SIO1028I-JZX integrates a full IrDA v1.2 Fast IR (4 Mbps) PHY within UART2, with dedicated IRTX2* and IRRX2*/IRRX3* pins and register-controlled mode selection. It also supports HPSIR, ASKIR, and Consumer IR protocols without external components. This capability is confirmed in the device block diagram and feature list of DS00001818A, distinguishing SIO1028I-JZX from Super I/Os requiring discrete IR transceivers.
How many UARTs does the SIO1028I-JZX provide, and what are their key capabilities?
The SIO1028I-JZX provides three independent NS16C550A-compatible UARTs. Each features 16-byte TX/RX FIFOs, programmable baud rate generators supporting up to 460 kbps, full modem control signals (nRTS/nCTS/nDTR/nDSR/nDCD/nRI), and individual interrupt assignment. UART2 additionally supports infrared communication via integrated IrDA v1.2 logic, as documented in DS00001818A pages 1–2 and Figure 1.
What package type and dimensions does the SIO1028I-JZX use?
The SIO1028I-JZX uses a 64-pin QFN package with 9 mm × 9 mm body size and 0.5 mm pin pitch, as shown in Figures 2 and 2 (continued) of DS00001818A. It includes an exposed thermal pad for improved heat dissipation and is RoHS compliant. This package is designated by the "JZX" suffix in the part number and is distinct from QFP or LQFP variants used by other Super I/O devices.
Is the SIO1028I-JZX 5 V tolerant, and how does that affect system design?
Yes, the SIO1028I-JZX operates at 3.3 V core voltage but features 5 V-tolerant I/O pins, allowing direct connection to legacy 5 V peripherals such as RS-232 level shifters or optocouplers without external voltage translators. This tolerance is explicitly stated in the Product Features section of DS00001818A and simplifies interface design in mixed-voltage notebook and industrial systems where 5 V signaling remains common.
SIO1028I-JZX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- Controller
- Interface:
- LPC
- Voltage - Supply:
- 3.3V
- Supplier Device Package:
- 64-QFN (9x9)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
SIO1028I-JZX FAQ
1.How can I place an order for SIO1028I-JZX through Aetrix?
Please submit a Request for Quotation (RFQ) for SIO1028I-JZX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIO1028I-JZX reliable?
The price and inventory of SIO1028I-JZX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIO1028I-JZX is usually 5 days.
3.What payment methods are accepted for SIO1028I-JZX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIO1028I-JZX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIO1028I-JZX?
SIO1028I-JZX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIO1028I-JZX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIO1028I-JZX?
For technical support, including SIO1028I-JZX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIO1028I-JZX requirements.
6.How does Aetrix verify that SIO1028I-JZX is sourced from the original manufacturer or authorized distributors?
All SIO1028I-JZX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIO1028I-JZX meets industry standards.
7.What is the process for return or replacement of SIO1028I-JZX?
All SIO1028I-JZX units undergo pre-shipment inspection (PSI). If there is an issue with SIO1028I-JZX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIO1028I-JZX part is unused and in its original packaging.
Return procedure for SIO1028I-JZX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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