Microchip Technology SIO1028-JZX
- Part No.:
- SIO1028-JZX
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
SIO1028-JZX.pdf
- Description:
- IC INTERFACE SPECIALIZED 64QFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,841
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Product details
Overview
SIO1028-JZX from Microchip Technology is a 64-pin QFN Super I/O controller supporting LPC bus interface at 19.2–33 MHz, three NS16C550A-compatible UARTs (including one with IrDA v1.2 infrared support), 24 GPIO pins, and ACPI 1.0 compliance - deployed in advanced notebook platforms requiring integrated serial, IR, and system management functions.
For engineers reviewing the SIO1028-JZX datasheet, SIO1028-JZX pinout, SIO1028-JZX application, or SIO1028-JZX equivalent, this device serves as a single-chip LPC I/O solution for embedded PC architectures needing high-speed serial communication, programmable wake-up events, watchdog timer output control, and dual LED driver support with blinking capability.
Technical Context
The SIO1028-JZX implements an LPC bus interface compliant with PC99/PC01 and ACPI 1.0 standards, featuring serial IRQ support and nIO_PME/nIO_SMI signal generation for system-level power management. Its block diagram confirms dedicated hardware paths for three UARTs, one of which integrates IRTX2/IRRX2 pins and supports IrDA v1.2 Fast IR (4 Mbps), HPSIR, ASKIR, and Consumer IR protocols.
It operates at 3.3 V with 5 V tolerant I/O, includes a clock generator accepting CLKI32 input, and provides configurable general-purpose I/O across GP[11:13], GP16, GP[20:23], GP[30:37], and GP[50:57] pins - all mapped to multifunction roles including UART control, IR signaling, and LED drive outputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LPC Bus Frequency | 19.2–33 MHz - defines maximum host-to-peripheral data throughput on legacy PC platform buses. |
| UART Count & Type | Three NS16C550A-compatible UARTs - enables simultaneous RS-232/RS-485 and infrared serial links with 16-byte FIFO buffering. |
| Infrared Support | IrDA v1.2 (4 Mbps), HPSIR, ASKIR, Consumer IR - allows bidirectional short-range wireless data exchange without external transceivers. |
| GPIO Pins | 24 general-purpose I/O - configurable as inputs, outputs, or multifunction signals (e.g., wake-up, interrupt, LED control). |
| Package | 64-pin QFN, 9 × 9 mm body, 0.5 mm pitch - surface-mount footprint optimized for space-constrained notebook motherboard layouts. |
| Power Supply | 3.3 V operation with 5 V tolerant I/O - simplifies level-shifting design and supports mixed-voltage peripheral interfacing. |
| Compliance | PC99, PC01, ACPI 1.0 - ensures interoperability with standard BIOS/firmware implementations in x86-based systems. |
Pinout & Package
64-pin QFN package, 9 × 9 mm body, 0.5 mm pitch, RoHS compliant - designed for reflow soldering and thermal dissipation in compact laptop mainboards.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LAD0–LAD3 | LPC Address/Data Bus | Time-multiplexed address and data lines for LPC protocol communication with host chipset. |
| LFRAME# | LPC Frame Signal | Indicates start/end of LPC transaction cycle; active-low synchronous control signal. |
| LDRQ# | LPC DMA Request | Initiates DMA transfers between SIO1028-JZX and host via LPC bus; active-low assertion. |
| TXD1/RXD1 | UART1 Transmit/Receive | Full-duplex asynchronous serial interface for primary COM port; 16-byte FIFO buffered. |
| IRTX2/IRRX2 | Infrared Transmit/Receive | Dedicated pins for IrDA v1.2 Fast IR physical layer signaling on UART2 channel. |
| LED1*/LED2* | LED Driver Outputs | Open-drain outputs supporting blinking patterns and polarity-controlled illumination for status indicators. |
| WDT* | Watchdog Timer Output | Active-low reset or interrupt signal triggered by timeout; configurable as reset or SMI assertion. |
| GP[11:13]* | General Purpose I/O | Configurable multifunction pins usable as wake-up sources, interrupt inputs, or GPIO under ACPI control. |
Key Features
| Feature | Design Value |
|---|---|
| Three UARTs with 16-byte FIFOs | Reduces CPU overhead and prevents data loss during high-baud-rate (up to 460 kbps) serial transfers. |
| Integrated IrDA v1.2 controller | Eliminates need for external IR transceiver ICs in notebook designs requiring wireless peripheral connectivity. |
| Programmable Wake-up Event (PME) | Enables selective system resume from S3/S4 states using GPIO, UART, or IR activity - critical for ACPI power management. |
| Dual LED drivers with blink logic | Offloads blinking timing control from host CPU, enabling autonomous status indication without firmware intervention. |
| System Management Interrupt (SMI) | Provides secure, high-priority interrupt path for BIOS-level system monitoring and configuration tasks. |
Applications
| Advanced Notebook I/O Hub | Legacy Serial Port Consolidation |
|---|---|
Use Scenario: Integration into thin-and-light laptop motherboards requiring minimal chip count for core I/O functionality. IC Role / Device Role / Timing Role: Central LPC-connected Super I/O controller managing UARTs, IR, GPIO, LED, and watchdog functions. Use Value: Reduces BOM cost and PCB area by replacing discrete UART, IR, and GPIO ICs with a single 64-pin QFN device. |
Use Scenario: Replacement of aging 16C550-based discrete UART solutions in industrial PCs requiring RS-232 compatibility. IC Role / Device Role / Timing Role: Drop-in-capable serial communications hub supporting up to 460 kbps baud rates and 16-byte FIFO buffering. Use Value: Maintains legacy software stack compatibility while adding infrared and ACPI-compliant power management features. |
| ACPI-Compliant System Monitoring | Embedded IR Remote Interface |
Use Scenario: Enabling S3/S4 sleep states in embedded x86 systems with reliable wake-on-event capability. IC Role / Device Role / Timing Role: ACPI 1.0-compliant PME and SMI source generating standardized power-state transition signals. Use Value: Guarantees BIOS-level interoperability for suspend/resume sequences without custom EC firmware development. |
Use Scenario: Adding infrared remote control support to kiosk or digital signage platforms using Consumer IR protocols. IC Role / Device Role / Timing Role: Hardware-accelerated IR encoder/decoder handling ASKIR and Consumer IR modulation schemes. Use Value: Offloads IR signal generation and demodulation from application processor, reducing real-time processing load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Super I/O controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IT8786E-S | 48-pin QFP package; supports LPC at up to 33 MHz but lacks IrDA v1.2 hardware acceleration. | Targeted at desktop motherboards with space tolerance; no native Fast IR support. | Choose when infrared capability is unnecessary and QFP assembly is preferred over QFN. |
| NCT6776D | 64-pin QFN package; adds hardware PWM fan control and temperature monitoring not present in SIO1028-JZX. | Designed for server/workstation thermal management; includes SMBus interface absent in SIO1028-JZX. | Prefer when fan speed regulation and multi-zone thermal sensing are required alongside serial I/O. |
Compared with IT8786E-S and NCT6776D, the SIO1028-JZX uniquely balances notebook-optimized footprint, integrated IrDA v1.2, and ACPI-compliant PME/SMI signaling - making it optimal for space-constrained mobile platforms where infrared connectivity and low-power wake-up are essential.
Availability
SIO1028-JZX is available at Aetrix Electronics and suitable for advanced notebook designs, embedded x86 platforms, and industrial PC applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for SIO1028-JZX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and interface ICs - with broad expertise in embedded control and system-level integration.
The SIO1028-JZX belongs to Microchip's Super I/O product line, engineered specifically for LPC-based PC architecture consolidation - delivering serial, infrared, GPIO, and power management functions in a single chip for notebook and embedded x86 platforms.
FAQ
What is the operating voltage range for the SIO1028-JZX?
The SIO1028-JZX operates at 3.3 V nominal supply voltage and features 5 V tolerant I/O pins. This allows direct interfacing with legacy 5 V peripherals without external level shifters, while maintaining compatibility with modern low-voltage motherboard power domains. The 3.3 V core operation reduces power consumption and thermal load in densely packed notebook designs.
Does the SIO1028-JZX support IrDA v1.2 at full 4 Mbps speed?
Yes, the SIO1028-JZX includes hardware-level IrDA v1.2 Fast IR support capable of 4 Mbps data transfer on its dedicated UART2 channel using IRTX2 and IRRX2 pins. This is confirmed in the device block diagram and functional description, enabling high-speed infrared communication without host CPU involvement in bit-level encoding.
How many UARTs does the SIO1028-JZX integrate, and what are their key capabilities?
The SIO1028-JZX integrates three independent NS16C550A-compatible UARTs. Each supports programmable baud rates up to 460 kbps, 16-byte send/receive FIFOs, modem control signals (nRTS/nCTS/nDTR/nDSR), and full RS-232/RS-485 framing. UART2 additionally supports infrared protocols via dedicated IRTX2/IRRX2 pins.
Is the SIO1028-JZX pin-compatible with earlier SMSC Super I/O devices?
No, the SIO1028-JZX is not pin-compatible with prior SMSC Super I/O devices such as the SMSC SCH5307 or SCH3112. It uses a unique 64-pin QFN layout defined in Microchip's DS00001818A datasheet, with distinct pin assignments for LPC signaling, UARTs, IR, and GPIO - requiring dedicated PCB layout.
What ACPI and industry standards does the SIO1028-JZX comply with?
The SIO1028-JZX complies with ACPI 1.0, PC99, and PC01 specifications. It implements standardized interfaces including nIO_PME for wake-up event signaling, nIO_SMI for system management interrupts, and LPC bus timing - ensuring interoperability with BIOS implementations across major x86 platform vendors.
SIO1028-JZX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- Controller
- Interface:
- LPC
- Voltage - Supply:
- 3.3V
- Supplier Device Package:
- 64-QFN (9x9)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
SIO1028-JZX FAQ
1.How can I place an order for SIO1028-JZX through Aetrix?
Please submit a Request for Quotation (RFQ) for SIO1028-JZX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIO1028-JZX reliable?
The price and inventory of SIO1028-JZX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIO1028-JZX is usually 5 days.
3.What payment methods are accepted for SIO1028-JZX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIO1028-JZX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIO1028-JZX?
SIO1028-JZX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIO1028-JZX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIO1028-JZX?
For technical support, including SIO1028-JZX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIO1028-JZX requirements.
6.How does Aetrix verify that SIO1028-JZX is sourced from the original manufacturer or authorized distributors?
All SIO1028-JZX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIO1028-JZX meets industry standards.
7.What is the process for return or replacement of SIO1028-JZX?
All SIO1028-JZX units undergo pre-shipment inspection (PSI). If there is an issue with SIO1028-JZX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIO1028-JZX part is unused and in its original packaging.
Return procedure for SIO1028-JZX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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