Microchip Technology SIO10N268-NU
- Part No.:
- SIO10N268-NU
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 128-TQFP
- Datasheet:
-
SIO10N268-NU.pdf
- Description:
- IC INTERFACE SPECIALIZED 128VTQN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SIO10N268-NU from Microchip Technology is a single-chip Super I/O controller supporting both ISA and LPC bus interfaces via jumper-selectable mode, operating at 3.3 V with 5 V tolerance, compliant with PC99/PC01 and ACPI 1.0 standards, and integrating a licensed CMOS 765B floppy disk controller, four NS16C550-compatible UARTs (including one with IrDA v1.2 infrared support), and a multi-mode parallel port with ChiProtect for notebook and embedded system designs.
For engineers reviewing the SIO10N268-NU datasheet, SIO10N268-NU pinout, SIO10N268-NU application, or SIO10N268-NU equivalent, this device serves as a legacy-compatible, RoHS-compliant I/O hub for industrial PCs, thin clients, and embedded controllers requiring integrated floppy, serial, parallel, and infrared connectivity with configurable power management and GPIO expansion.
Technical Context
The SIO10N268-NU implements dual-bus architecture: in ISA mode, it supports Plug-and-Play configuration with reprogrammable I/O address, DMA channel, and IRQ assignments; in LPC mode, it enables X-Bus interface for external 8-bit I/O devices and up to 2 MB of ISA memory-mapped flash, including Firmware Hub (FWH) emulation. Its clock generation supports 32 kHz and system clock inputs.
It integrates a true CMOS 765B floppy controller with vertical recording format support, 16-byte FIFO, and sophisticated power control circuitry (PCC) enabling multiple power-down modes; the four UARTs each feature 16-byte send/receive FIFOs, programmable baud rates up to 460 kbps, and full modem control signals - with UART2 extended for IrDA v1.2 (4 Mbps), HPSIR, ASKIR, and Consumer IR protocols.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Bus Interface | LPC or ISA (jumper-selectable); enables hardware-level migration path between legacy and modern platform architectures |
| Supply Voltage | 3.3 V operation with 5 V tolerant I/O; allows direct interfacing with mixed-voltage system components without level shifters |
| Floppy Controller | Licensed CMOS 765B core, 16-byte FIFO, vertical recording support, 100% IBM compatibility; eliminates need for discrete FDC IC |
| Serial Ports | Four NS16C550-compatible UARTs; UART2 includes IrDA v1.2, HPSIR, ASKIR, and Consumer IR transceivers on dedicated pins |
| Parallel Port | Multi-mode (SPP/EPP 1.7–1.9/ECP), IEEE 1284 compliant, with ChiProtect ESD circuitry; supports legacy printers and high-speed data transfer peripherals |
| GPIO Pins | 33 general-purpose I/O pins with configurable drive strength and interrupt capability; provides flexible board-level control and monitoring |
| Package | 128-pin VTQN (14 × 14 × 1.0 mm body, 0.4 mm pitch); RoHS-compliant QFN with exposed thermal pad for thermal management |
Pinout & Package
Package: 128-pin VTQN (Very Thin Quad Flat No-Lead), RoHS-compliant, 14 mm × 14 mm × 1.0 mm body, 0.4 mm lead pitch, exposed thermal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Vcc / Vss | Power / Ground | Dedicated 3.3 V supply and ground pins distributed across package corners for low-noise power delivery |
| XD[0:7] | X-Bus Data Bus | 8-bit bidirectional data path for external I/O or memory devices in LPC mode only |
| XA[0:18] | X-Bus Address Bus | 19-bit address lines supporting up to 2 MB memory mapping in LPC/X-Bus mode |
| nXCS0–nXCS2 | X-Bus Chip Selects | Three independent chip selects: two for I/O devices, one for memory or FWH flash |
| TXD2 / IRTX2* | Infrared Transmit | Dual-function pin: UART2 transmit output or active-low IrDA fast IR driver (4 Mbps) |
| RXD2 / IRRX2* | Infrared Receive | Dual-function pin: UART2 receive input or active-low IrDA receiver with internal signal conditioning |
| GP[30:37]* | General Purpose I/O | Eight multifunction GPIO pins supporting interrupt, pull-up/down, and open-drain/push-pull configuration |
Key Features
| Feature | Design Value |
|---|---|
| LPC/ISA Mode Selection | Jumper-configurable bus interface enables reuse of same PCB layout across ISA-to-LPC platform transitions |
| Firmware Hub Emulation | Enables direct connection to standard 3 V SPI/NOR flash for BIOS storage without external bridge logic |
| IrDA v1.2 + Consumer IR Support | Single UART (UART2) delivers interoperable infrared communication across PC, remote control, and consumer electronics ecosystems |
| ChiProtect Parallel Port | Integrated ESD protection on all parallel port pins meets IEC 61000-4-2 Level 4 (±15 kV air, ±8 kV contact) |
| Programmable Wake-up Event (PME) | Hardware-level wake signal generation from GPIO, serial, or floppy activity - critical for ACPI S3/S4 resume compliance |
Applications
| Industrial Thin Client | Legacy-Embedded Control Panel |
|---|---|
Use Scenario: Fanless x86-based thin client deployed in factory automation with space-constrained PCB and requirement for floppy boot media, serial diagnostics, and parallel printer support. IC Role / Device Role / Timing Role: Centralized I/O hub managing floppy boot sequence, four RS-232 debug ports, ECP parallel printer interface, and ACPI-compliant power state transitions. Use Value: Eliminates six discrete ICs (FDC, UARTs, parallel controller, IR transceiver, GPIO expander, PME generator), reducing BOM cost and layout area by >40%. |
Use Scenario: Human-machine interface (HMI) panel in medical equipment requiring secure local firmware update via floppy, serial service port, and infrared remote pairing. IC Role / Device Role / Timing Role: Trusted peripheral controller handling secure floppy-based firmware loading, isolated UART2 infrared handshake, and watchdog-triggered safe shutdown. Use Value: Enables certified Class II medical device compliance through integrated PCC power management, ChiProtect ESD hardening, and deterministic WDT timeout behavior. |
| ACPI-Compliant Notebook Baseboard | PCI-Based Industrial Server Management |
Use Scenario: Low-power notebook baseboard needing ACPI 1.0-compliant suspend/resume, LED status indicators, and floppy-based BIOS recovery. IC Role / Device Role / Timing Role: System management controller providing SMI/PME signaling, blinking LED drivers, and floppy controller with vertical recording for high-density media support. Use Value: Meets PC99/PC01 certification requirements with zero additional logic; 33 GPIOs enable OEM-specific status reporting and button debouncing. |
Use Scenario: Rack-mounted server with PCI backplane requiring serialized IRQ routing, watchdog supervision, and out-of-band serial console access. IC Role / Device Role / Timing Role: LPC-attached management I/O companion to BMC, delivering Serial IRQ aggregation, WDT reset assertion, and four independent UART console channels. Use Value: Provides hardware-level IRQ serialization compatible with PCI specification, eliminating software polling overhead and ensuring deterministic interrupt latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Super I/O controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SMSC SIO10N267-NU | Identical pinout and register map but lacks IrDA v1.2 support; UART2 is standard NS16C550 only | No infrared capability; suitable where IR is unused and cost reduction is prioritized | Select SIO10N267-NU only if infrared functionality is excluded from design scope |
| Winbond W83627DHG-P | 128-pin LQFP package (not VTQN); supports LPC-only interface; no ISA mode or X-Bus; adds hardware monitor and fan control | Requires PCB redesign due to different footprint and missing ISA/X-Bus; targets modern LPC-only systems with thermal monitoring needs | Choose W83627DHG-P only when migrating fully to LPC architecture and requiring integrated hardware monitoring |
Compared with SIO10N268-NU, the SIO10N267-NU removes infrared capability while preserving full ISA/LPC flexibility and pin compatibility, whereas the W83627DHG-P abandons ISA and X-Bus entirely in favor of enhanced system monitoring - making SIO10N268-NU uniquely suited for transitional or infrared-dependent legacy platforms.
Availability
SIO10N268-NU is available at Aetrix Electronics and suitable for industrial thin clients, legacy-embedded control panels, and ACPI-compliant notebook baseboards requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.
Supply support for SIO10N268-NU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and connectivity solutions, with global design, manufacturing, and support infrastructure.
The SIO10N268-NU belongs to Microchip's Advanced Notebook I/O product line, designed specifically to consolidate legacy PC peripheral functions - floppy, serial, parallel, infrared, and power management - into a single, ACPI-compliant, migration-ready Super I/O controller.
FAQ
What bus interface modes does the SIO10N268-NU support?
The SIO10N268-NU supports both LPC and ISA bus interfaces, selected via hardware jumper. In LPC mode, it enables X-Bus for external I/O/memory and FWH emulation; in ISA mode, it complies with Plug-and-Play v1.0a and allows reprogramming of I/O address, DMA, and IRQ settings via internal registers - making SIO10N268-NU ideal for platform migration projects.
Does the SIO10N268-NU include infrared communication capability?
Yes, the SIO10N268-NU integrates IrDA v1.2 (4 Mbps), HPSIR, ASKIR, and Consumer IR support exclusively on UART2, using dedicated IRTX2* and IRRX2* pins. This enables interoperable infrared communication without external transceivers - a key differentiator versus non-infrared Super I/O variants like the SIO10N267-NU.
What is the function of the X-Bus interface in the SIO10N268-NU?
The X-Bus interface in the SIO10N268-NU is active only in LPC mode and provides an 8-bit data bus (XD[0:7]), 19-bit address bus (XA[0:18]), three chip selects (nXCS0–nXCS2), and control signals (nXRD/nXWR) to connect external I/O peripherals or up to 2 MB of 3 V memory - enabling BIOS flash integration and expansion without additional glue logic.
Is the SIO10N268-NU RoHS compliant and what package does it use?
Yes, the SIO10N268-NU is RoHS compliant and packaged in a 128-pin VTQN (Very Thin Quad Flat No-Lead) package measuring 14 mm × 14 mm × 1.0 mm with 0.4 mm pitch and an exposed thermal pad - confirmed in Microchip's DS00001819A datasheet and packaging specification documents.
How many serial ports does the SIO10N268-NU provide and what are their capabilities?
The SIO10N268-NU provides four full-function NS16C550-compatible UARTs, each with 16-byte send/receive FIFOs and programmable baud rates up to 460 kbps. UART2 includes integrated IrDA v1.2, HPSIR, ASKIR, and Consumer IR transceivers, while all UARTs support full modem control signals (RTS/CTS/DTR/DSR/DCD/RI) and 480 I/O address options.
SIO10N268-NU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 128-TQFP
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- Notebook Computer
- Interface:
- LPC
- Voltage - Supply:
- 3.3V
- Supplier Device Package:
- 128-VTQFP (14x14)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
SIO10N268-NU FAQ
1.How can I place an order for SIO10N268-NU through Aetrix?
Please submit a Request for Quotation (RFQ) for SIO10N268-NU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIO10N268-NU reliable?
The price and inventory of SIO10N268-NU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIO10N268-NU is usually 5 days.
3.What payment methods are accepted for SIO10N268-NU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIO10N268-NU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIO10N268-NU?
SIO10N268-NU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIO10N268-NU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIO10N268-NU?
For technical support, including SIO10N268-NU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIO10N268-NU requirements.
6.How does Aetrix verify that SIO10N268-NU is sourced from the original manufacturer or authorized distributors?
All SIO10N268-NU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIO10N268-NU meets industry standards.
7.What is the process for return or replacement of SIO10N268-NU?
All SIO10N268-NU units undergo pre-shipment inspection (PSI). If there is an issue with SIO10N268-NU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIO10N268-NU part is unused and in its original packaging.
Return procedure for SIO10N268-NU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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