Vishay Siliconix SIP21106DT-285-E3
- Part No.:
- SIP21106DT-285-E3
- Manufacturer:
- Vishay Siliconix
- Package:
- SOT-23-5 Thin, TSOT-23-5
- Datasheet:
-
SIP21106DT-285-E3.pdf
- Description:
- IC REG LIN 2.85V 150MA TSOT23-5
- Quantity:
- Payment:

- Shipping:

Inventory:3,263
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Product details
Overview
SIP21106DT-285-E3 from Vishay Siliconix is a fixed-output 2.85 V, 150 mA low-noise low-dropout (LDO) regulator in TSOT23-5L package. It features 135 mV dropout at full load, 60 µV(rms) output noise (10 Hz–100 kHz), and 35 µA ground current at 1 mA - optimized for battery-powered RF systems requiring stable, quiet voltage rails.
For engineers reviewing the SIP21106DT-285-E3 datasheet, SIP21106DT-285-E3 pinout, SIP21106DT-285-E3 application, or SIP21106DT-285-E3 equivalent, key selection criteria include ultra-low noise performance, auto-discharge capability during shutdown, fixed 2.85 V output with ±1.0 % room-temperature accuracy, and compatibility with 1 µF ceramic output capacitors.
Technical Context
The SIP21106DT-285-E3 uses a P-channel MOSFET pass transistor with 0.9 Ω typical on-resistance, enabling low quiescent current and no base-drive loss. Its bandgap reference (1.2 V) and error amplifier maintain regulation across -40 °C to +85 °C ambient, with internal thermal shutdown at 160 °C and short-circuit protection up to 330 mA.
Startup includes an active pull-down circuit for improved transient response; shutdown mode activates a 100 Ω NMOS discharge path to ground, discharging a 1 µF capacitor in <1 ms. The BP pin accepts a 10 nF bypass capacitor to reduce output noise without compromising stability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 2.85 V ±1.0 % at 25 °C; ensures precise biasing for 2.85 V logic or RF ICs without external feedback. |
| Dropout Voltage | 135 mV at 150 mA load; enables operation down to VIN = 2.985 V while maintaining regulation - critical for single-cell Li-ion or alkaline systems. |
| Output Noise | 60 µV(rms), 10 Hz–100 kHz bandwidth with 10 nF BP capacitor; meets stringent RF supply noise requirements (e.g., LNA, mixer, PLL VCO rails). |
| Ground Current | 35 µA typical at 1 mA load; extends battery life in standby or low-power sleep modes of portable devices. |
| Shutdown Current | ≤1 µA maximum at 85 °C; minimizes leakage drain during system hibernation. |
| Auto-Discharge | 100 Ω internal NMOS discharge path; safely clears output capacitance within 1 ms after EN deactivation - prevents unintended wake-up or latch-up. |
| Thermal Protection | 160 °C junction shutdown with 20 °C hysteresis; prevents permanent damage during sustained overload or poor PCB thermal design. |
Pinout & Package
TSOT23-5L package (3.05 mm × 2.85 mm × 1.0 mm), RoHS-compliant, rated for -40 °C to +85 °C ambient operation.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 (EN) | Enable input | Active-high control: ≥1.2 V enables regulation; ≤0.4 V disables output and triggers auto-discharge. |
| 2 (GND) | Power ground | Primary thermal and electrical return path; must connect to large copper plane for thermal dissipation and noise reduction. |
| 3 (VIN) | Input supply | Accepts 2.2–6.0 V input; requires 1 µF ceramic bypass capacitor close to pin for line-transient immunity. |
| 4 (VOUT) | Regulated output | Delivers stable 2.85 V; supports 1 µF ceramic output capacitor for full-load stability and fast load-transient response. |
| 5 (BP) | Noise bypass | Connects to 10 nF ceramic capacitor to ground; forms low-pass filter that reduces output noise by >10× vs. no-BP configuration. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low output noise | 60 µV(rms) with 10 nF BP cap - enables direct powering of noise-sensitive RF front-end components without additional filtering. |
| Low dropout architecture | 135 mV @ 150 mA using P-MOS pass element - eliminates base-current losses inherent in PNP-based LDOs, improving efficiency at light loads. |
| Integrated auto-discharge | 100 Ω NMOS discharge switch activated on EN low - removes need for external bleed resistor, saving board space and BOM cost. |
| Stable with small ceramics | Guaranteed stability with ≥1 µF X7R/Y7R ceramic output capacitor - avoids bulky tantalum or electrolytic caps and simplifies layout. |
| Robust protection suite | 330 mA current limit + 160 °C thermal shutdown + 125 °C max continuous junction temperature - supports reliable operation under fault conditions. |
Applications
| Cellular RF Power Amplifier Bias | Portable Audio Codec Supply |
|---|---|
Use Scenario: Providing clean bias voltage to GaAs pHEMT power amplifiers in 3G/4G handset front-ends. IC Role / Device Role / Timing Role: Low-noise LDO delivering stable 2.85 V to PA collector rail, minimizing AM-to-PM distortion and adjacent channel leakage. Use Value: 60 µV(rms) noise ensures EVM compliance; 135 mV dropout preserves headroom during battery sag, sustaining PA efficiency down to 3.0 V input. | Use Scenario: Supplying analog core of stereo audio codec in Bluetooth headphones or voice-controlled wearables. IC Role / Device Role / Timing Role: Fixed 2.85 V LDO powering DAC/ADC reference and analog I/O stages, rejecting digital switching noise from shared SoC domain. Use Value: BP-capacitor filtered output suppresses 1/f and broadband noise, lowering THD+N below 0.005 %; 35 µA ground current extends playback time per charge. |
| Digital Camera Image Sensor Core | Wireless Modem Baseband Processor |
Use Scenario: Powering CMOS image sensor analog pixel array and column ADC in compact digital cameras or action cams. IC Role / Device Role / Timing Role: Primary 2.85 V analog rail LDO with fast transient response to handle burst readout current spikes up to 150 mA. Use Value: Active pull-down circuit improves turn-on transient settling to <70 µs; 1 µF ceramic compatibility enables miniaturized camera module designs. | Use Scenario: Supplying 2.85 V I/O or memory interface voltage for LTE/Wi-Fi baseband processors in M2M modules. IC Role / Device Role / Timing Role: Secondary LDO decoupling high-speed digital interfaces from noisy system rails, supporting 1.8 V/2.85 V dual-voltage I/O standards. Use Value: 75 dB PSRR at 1 kHz rejects coupled noise from switching regulators; shutdown current <1 µA meets deep-sleep power budgets for cellular IoT. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MCP1700T-285I/OT | 300 mA rated, 170 mV dropout at 250 mA, 30 µV(rms) noise, SOT23-5 package | Lacks BP pin and auto-discharge; requires external discharge resistor for safe shutdown | Select when higher output current or lower noise is prioritized over integrated discharge and BP filtering. |
| TCS21106DVP-285-E3 | Same SiP21106 family, TSC75-6L package (1.6 mm × 1.6 mm), identical electrical specs | Smaller footprint but different pinout (6-pin, NC pin); requires PCB redesign | Select when board space is constrained and thermal resistance <131 °C/W is required for high-ambient environments. |
Compared with MCP1700T-285I/OT and TCS21106DVP-285-E3, the SIP21106DT-285-E3 uniquely combines BP-enabled ultra-low noise, integrated auto-discharge, and TSOT23-5L manufacturability - making it optimal for RF-critical, space-constrained, battery-operated designs where startup/shutdown behavior and noise floor are non-negotiable.
Availability
SIP21106DT-285-E3 is available at Aetrix Electronics and suitable for cellular handsets, wireless modems, and digital cameras requiring stable component supply despite its End-of-Life status per Vishay's last purchase date of 31-Dec-2014.
Supply support for SIP21106DT-285-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix designs high-performance discrete semiconductors and integrated power solutions, emphasizing reliability, efficiency, and miniaturization for demanding electronic systems.
The SiP21106 product line delivers ultra-low-noise, low-quiescent-current LDOs specifically engineered for battery-powered RF and portable consumer electronics where power integrity directly impacts signal fidelity and runtime.
FAQ
What is the output voltage tolerance of SIP21106DT-285-E3 over temperature?
The SIP21106DT-285-E3 maintains ±2.5 % output voltage accuracy across the full operating temperature range of -40 °C to +85 °C. At room temperature (25 °C), the tolerance tightens to ±1.0 %. This ensures consistent biasing for 2.85 V logic and analog circuits even under thermal stress, as confirmed in the "Output Voltage Accuracy" specification table of Vishay Document 74442.
Does SIP21106DT-285-E3 require an external bypass capacitor on the BP pin?
Yes, SIP21106DT-285-E3 requires a 10 nF ceramic capacitor between the BP pin and ground to achieve its specified 60 µV(rms) output noise performance. Omitting this capacitor increases noise to ~350 µV(rms). The BP pin is not used for stability compensation - it solely filters high-frequency noise via a dedicated internal low-pass path, as detailed in the "Noise Reduction in SiP21106" section of the datasheet.
Can SIP21106DT-285-E3 be used with a 0.47 µF output capacitor?
No - SIP21106DT-285-E3 is only guaranteed stable with ≥1 µF ceramic output capacitance (X7R/Y7R dielectric recommended). Using 0.47 µF violates the minimum 6 nF/mA rule (≥900 nF for 150 mA load) and risks oscillation or degraded load-transient response, as explicitly stated in the "Input/Output Capacitor Selection" application note of Document 74442.
What happens to the output of SIP21106DT-285-E3 when the EN pin is pulled low?
When the EN pin voltage drops below 0.4 V, SIP21106DT-285-E3 enters shutdown mode: the output disconnects from the pass transistor and is actively discharged to ground through an internal 100 Ω NMOS switch. This clears VOUT to near 0 V within 1 ms for a 1 µF load, preventing residual voltage from interfering with downstream logic states or causing unintended wake-up events.
Is SIP21106DT-285-E3 compatible with lead-free reflow soldering profiles?
Yes, SIP21106DT-285-E3 is RoHS-compliant and qualified for standard lead-free reflow soldering per JEDEC J-STD-020. Its TSOT23-5L package supports peak temperatures up to 260 °C for 5 seconds, as verified in the "Absolute Maximum Ratings" table of Document 74442. No special preheat or cooling ramp rates are required beyond industry-standard Pb-free profiles.
SIP21106DT-285-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Package/Case:
- SOT-23-5 Thin, TSOT-23-5
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 2.85V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.22V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 85 µA
- Current - Supply (Max):
- -
- PSRR:
- 75dB ~ 40dB (1kHz ~ 100kHz)
- Control Features:
- Enable
- Protection Features:
- Over Temperature, Short Circuit
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- TSOT-23-5
SIP21106DT-285-E3 FAQ
1.How can I place an order for SIP21106DT-285-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIP21106DT-285-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIP21106DT-285-E3 reliable?
The price and inventory of SIP21106DT-285-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIP21106DT-285-E3 is usually 5 days.
3.What payment methods are accepted for SIP21106DT-285-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIP21106DT-285-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIP21106DT-285-E3?
SIP21106DT-285-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIP21106DT-285-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIP21106DT-285-E3?
For technical support, including SIP21106DT-285-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIP21106DT-285-E3 requirements.
6.How does Aetrix verify that SIP21106DT-285-E3 is sourced from the original manufacturer or authorized distributors?
All SIP21106DT-285-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIP21106DT-285-E3 meets industry standards.
7.What is the process for return or replacement of SIP21106DT-285-E3?
All SIP21106DT-285-E3 units undergo pre-shipment inspection (PSI). If there is an issue with SIP21106DT-285-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIP21106DT-285-E3 part is unused and in its original packaging.
Return procedure for SIP21106DT-285-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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