NXP Semiconductors SJA1000T/N1,118

Overview

SJA1000T/N1,118 from NXP Semiconductors (formerly Philips) is a stand-alone CAN 2.0B controller IC designed for automotive and industrial embedded networks. It supports both standard (11-bit) and extended (29-bit) frame formats, operates up to 1 Mbit/s bit rate, features a 64-byte receive FIFO, and delivers −40 °C to +125 °C operating temperature range - deployed in vehicle body control modules and factory automation gateways.

For engineers reviewing the SJA1000T/N1,118 datasheet, SJA1000T/N1,118 pinout, SJA1000T/N1,118 application, or SJA1000T/N1,118 equivalent, key selection considerations include PeliCAN vs. BasicCAN mode register mapping, programmable error warning limit (EWLR), dual-mode clock divider configuration (CDR), and hardware-level CAN bus-off recovery timing.

Technical Context

The SJA1000T/N1,118 implements two distinct operational modes: BasicCAN (PCA82C200-compatible default) and PeliCAN (full CAN 2.0B support). Its Bit Stream Processor (BSP) handles arbitration, stuffing, and error detection, while Bit Timing Logic (BTL) provides programmable synchronization jump width (SJW), time segments (TSEG1/TSEG2), and sample point control via BTR0/BTR1 registers.

Interface Management Logic (IML) manages CPU access across Intel/Motorola bus protocols using ALE/AS and RD/E/WR signals. The 24 MHz oscillator input drives CLKOUT (programmable divider output), and dual CAN transceiver outputs TX0/TX1 interface with external physical layer drivers, while RX0/RX1 accept differential bus signals - with optional internal comparator bypass (CBP bit) for reduced latency when using external transceivers.

Key Specifications

Pinout & Package

SO28 plastic small outline package (body width 7.5 mm, SOT136-1); 28-pin surface-mount device with gull-wing leads, RoHS-compliant, rated for reflow and wave soldering per JEDEC J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CAN controller applications.

Compared with MCP2515-I/SO, the SJA1000T/N1,118 offers direct parallel bus integration and advanced PeliCAN diagnostics, while TJA1042TK/3 serves a complementary PHY role rather than substituting controller functionality - making SJA1000T/N1,118 irreplaceable in legacy microcontroller-based CAN node designs requiring hardware-level protocol offload.

Availability

SJA1000T/N1,118 is available at Aetrix Electronics and suitable for automotive body control units, industrial PLC gateways, and off-highway telematics systems requiring stable component supply across extended product lifecycles.

Supply support for SJA1000T/N1,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep heritage in CAN technology dating to Philips' original PCA82C200.

The SJA1000T/N1,118 belongs to NXP's legacy CAN controller product line, engineered specifically for high-reliability embedded systems requiring software-compatible migration from PCA82C200 and enhanced diagnostics for functional safety-aware architectures.

FAQ

What is the primary function of the SJA1000T/N1,118 in a CAN network?

The SJA1000T/N1,118 serves as a stand-alone CAN 2.0B protocol controller that handles message framing, arbitration, error detection, and bus timing - offloading these tasks from the host microcontroller. It manages transmit/receive buffers, implements acceptance filtering, and supports both BasicCAN (PCA82C200-compatible) and PeliCAN (extended feature) modes. The SJA1000T/N1,118 does not include a physical layer; it requires an external CAN transceiver for bus connection.

Does the SJA1000T/N1,118 support both standard and extended CAN frames?

Yes, the SJA1000T/N1,118 supports both 11-bit standard and 29-bit extended CAN frames - but only in PeliCAN mode. In default BasicCAN mode, it transmits and receives standard frames only; extended frames are tolerated (acknowledged if valid) but do not trigger receive interrupts. The SJA1000T/N1,118 enters PeliCAN mode via the CAN-mode bit in the Clock Divider Register (CDR), enabling full CAN 2.0B compliance including extended identifier handling and associated registers like ALC and EWLR.

How does the SJA1000T/N1,118 handle bus-off recovery?

The SJA1000T/N1,118 initiates automatic bus-off recovery upon clearing the Reset Request (RR) bit in the Control Register (CR.0). After RR transitions from 1 to 0, it waits for either one bus-free sequence (11 recessive bits) following a hardware or software reset, or 128 bus-free sequences after a bus-off event. During this period, internal registers are reinitialized per Table 2 of the datasheet. The SJA1000T/N1,118 does not require external intervention beyond RR bit control - no dedicated recovery timer or watchdog is needed.

Can the SJA1000T/N1,118 operate with a microcontroller using Motorola bus protocol?

Yes, the SJA1000T/N1,118 supports Motorola bus protocol via the MODE pin (pin 11): logic LOW selects Motorola mode, configuring RD/E as E-enable and WR as RD/WR. Address/data multiplexing remains identical, but timing and strobe behavior align with 68K-family microcontrollers. The SJA1000T/N1,118 maintains full register compatibility and functional equivalence between Intel and Motorola modes - only control signal interpretation differs. Both modes support all PeliCAN and BasicCAN features.

What is the purpose of the CBP bit in the Clock Divider Register of the SJA1000T/N1,118?

Setting the CBP (CAN Bypass) bit in the Clock Divider Register (CDR) disables the internal CAN input comparator, allowing direct connection of RX0 to an external transceiver's logic-level output. This reduces internal propagation delay - critical for high-bit-rate or low-latency applications. When CBP = 1, only RX0 is active (RX1 is ignored), and logic HIGH/LOW directly represent recessive/dominant bus states. The SJA1000T/N1,118 retains full protocol processing capability; only the analog front-end is bypassed.