NXP Semiconductors SJA1000T/N,112
- Part No.:
- SJA1000T/N,112
- Manufacturer:
- NXP Semiconductors
- Category:
- Controllers
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
SJA1000T/N,112.pdf
- Description:
- IC STAND-ALONE CAN CTRLR 28-SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,697
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SJA1000T/N,112 from NXP Semiconductors (formerly Philips) is a stand-alone CAN 2.0B controller IC designed for automotive and industrial embedded networks. It supports both standard (11-bit) and extended (29-bit) frame formats, operates up to 1 Mbit/s, features a 64-byte receive FIFO, and interfaces directly with 8-bit microcontrollers via multiplexed AD0–AD7 bus. It is used in vehicle body control modules and industrial PLC backplanes.
For engineers reviewing the SJA1000T/N,112 datasheet, SJA1000T/N,112 pinout, SJA1000T/N,112 application, or SJA1000T/N,112 equivalent, key selection considerations include PeliCAN mode register access, dual-mode compatibility (BasicCAN/PeliCAN), programmable bit timing (BTR0/BTR1), CLKOUT configurability, and RX/TX driver output control via OCR.
Technical Context
The SJA1000T/N,112 implements two distinct operational modes: BasicCAN (PCA82C200-compatible) and PeliCAN (full CAN 2.0B). In BasicCAN mode, it emulates legacy register mapping and supports only 11-bit identifiers; in PeliCAN mode, it exposes extended registers including TXERR/RXERR error counters, IER interrupt enable, and RBSA receive buffer start address. Both modes share the same physical interface logic and BSP/BTL/EML core blocks.
Its Bit Timing Logic (BTL) provides programmable synchronization jump width (SJW), baud rate prescaler (BRP), and time segment configuration (TSEG1/TSEG2) to meet ISO 11898-1 timing requirements across temperature and cable length variations. The Interface Management Logic (IML) supports Intel- and Motorola-style microcontroller buses via MODE pin selection and ALE/AS, RD/E, WR control signals.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CAN Protocol | CAN 2.0B compliant - supports both 11-bit standard and 29-bit extended frames in PeliCAN mode; tolerates extended frames passively in BasicCAN mode. |
| Max Bit Rate | 1 Mbit/s - enables high-speed communication in powertrain and chassis networks without requiring external arbitration logic. |
| Receive Buffer | 64-byte RX FIFO - allows CPU to process one message while up to 64 bytes of subsequent messages are buffered, reducing overrun risk in burst-traffic scenarios. |
| Bus Interface | 8-bit multiplexed AD0–AD7 with ALE/AS, RD/E, WR, CS - compatible with common 80C51, 68HC11, and Z80-based controllers without glue logic. |
| Operating Temp | −40 °C to +125 °C - qualified for under-hood automotive environments and industrial control cabinets with wide thermal cycling. |
| Supply Voltages | VDD1/VDD2/VDD3 = 5 V ±10% - separate supplies for logic (VDD1/VSS1), input comparator (VDD2/VSS2), and CAN drivers (VDD3/VSS3) enable noise isolation and flexible PCB layout. |
| Crystal Frequency | 24 MHz - drives internal oscillator; supports programmable clock division (CDR) to generate CLKOUT for synchronizing host MCU peripherals. |
Pinout & Package
Package: SO28 (plastic small outline, 28 leads, 7.5 mm body width, SOT136-1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AD0–AD7 | Multiplexed address/data bus | Shared 8-bit bidirectional path for register access and message data transfer; requires external latch (e.g., 74HC373) in Intel mode. |
| ALE/AS | Address latch enable / address strobe | Demultiplexes AD0–AD7 in Intel mode (ALE pulse); serves as address strobe in Motorola mode (AS active-low). |
| CS | Chip select | Active-low enable for register access; must be asserted during all read/write cycles to SJA1000T/N,112. |
| RD/E, WR | Read/enable or write control | RD/E functions as read signal (Intel) or E-enable (Motorola); WR is write signal (Intel) or combined RD/WR (Motorola). |
| CLKOUT | Programmable clock output | Provides divided oscillator signal (e.g., 12 MHz, 6 MHz) to synchronize host MCU; disabled via CDR clock-off bit. |
| MODE | Bus protocol select | High = Intel mode (80C51-style), Low = Motorola mode (68HC11-style); determines control signal interpretation. |
| INT | Open-drain interrupt output | Active-low wired-OR interrupt signaling; asserts on any enabled condition (RX, TX, error, overrun); wakes MCU from sleep. |
| RST | Reset input | Active-low asynchronous reset; supports automatic power-on reset via RC network (e.g., 1 µF + 50 kΩ). |
| TX0, TX1 | CAN driver outputs | Differential outputs driving external CAN transceiver (e.g., PCA82C250); polarity and drive strength configured via OCR register. |
| RX0, RX1 | CAN receiver inputs | Differential inputs from transceiver; bypassable via CDR.CBP bit when external comparator is used, reducing propagation delay. |
Key Features
| Feature | Design Value |
|---|---|
| PeliCAN mode extensions | Enables full CAN 2.0B support including 29-bit ID handling, error counters with read/write access, and arbitration lost capture with bit-position detail - critical for diagnostic and safety-critical systems. |
| Single-shot transmission | Disables automatic retransmission after error or arbitration loss - prevents bus flooding and supports deterministic message scheduling in real-time control loops. |
| Listen-only mode | Permits passive monitoring of CAN traffic without transmitting ACKs or error flags - essential for debugging, logging, and gateway snooping applications. |
| Hot-plug bit-rate detection | Software-driven auto-detection of bus bit rate during insertion - eliminates manual configuration and enables plug-and-play node deployment in modular systems. |
| Programmable output driver | OCR register configures TX0/TX1 polarity, slew rate, and driver type (push-pull/open-drain) - allows optimization for EMC, cable length, and transceiver compatibility. |
Applications
| Automotive Body Control Unit | Industrial PLC Backplane |
|---|---|
Use Scenario: Centralized control of door locks, lighting, HVAC, and window motors via distributed CAN nodes. IC Role / Device Role / Timing Role: Stand-alone CAN controller managing message filtering, buffering, and error handling between MCU and physical layer. Use Value: 64-byte RX FIFO prevents message loss during high-priority interrupt servicing; PeliCAN mode enables firmware updates over extended-frame diagnostics. | Use Scenario: Interconnecting I/O modules, motion controllers, and HMI panels in factory automation systems. IC Role / Device Role / Timing Role: Protocol engine implementing ISO 11898-1 framing, bit timing, and error confinement for deterministic fieldbus communication. Use Value: Programmable BTR0/BTR1 registers allow precise bit timing calibration across long cable runs; −40 °C to +125 °C rating ensures reliability in unconditioned control cabinets. |
| Off-Highway Vehicle Telematics | Medical Equipment Data Bus |
Use Scenario: Aggregating sensor data (engine temp, hydraulic pressure, GPS) and transmitting to remote fleet management servers. IC Role / Device Role / Timing Role: CAN interface bridging microcontroller to isolated CAN transceiver, supporting hot-plug node discovery and robust error recovery. Use Value: Listen-only mode enables non-intrusive data capture for regulatory logging; single-shot transmission avoids bus contention during critical fault reporting. | Use Scenario: Synchronizing infusion pumps, monitors, and imaging devices within hospital networks requiring EMI resilience and functional safety. IC Role / Device Role / Timing Role: Timing-critical CAN node controller ensuring deterministic latency for alarm and control messaging. Use Value: Error Management Logic (EML) with ECC and EWLR registers supports IEC 62304 Class C software verification; extended temperature range accommodates sterilization cycles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar CAN controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MCP2515-I/SO | SPI interface instead of parallel bus; no native BasicCAN mode; requires external crystal (up to 25 MHz); lacks listen-only mode and hot-plug detection. | Better suited for space-constrained designs with SPI-capable MCUs; not drop-in replaceable due to interface and register architecture differences. | Select MCP2515-I/SO when migrating to modern microcontrollers with SPI peripherals and when PCB layout favors serial interface over parallel bus routing. |
| TJA1050T/CM | Physical-layer transceiver only - no CAN protocol logic; requires external controller (e.g., SJA1000T/N,112 or MCU with CAN peripheral); 5 V supply, high-speed CAN compliant. | Used downstream of SJA1000T/N,112 as its bus driver; not functionally equivalent - serves complementary role in the signal chain. | Select TJA1050T/CM only as a companion transceiver; never as a functional replacement for SJA1000T/N,112's controller functionality. |
Compared with MCP2515-I/SO and TJA1050T/CM, the SJA1000T/N,112 uniquely delivers parallel-microcontroller integration, dual-mode CAN protocol support, and hardware-level features like listen-only operation and hot-plug bit-rate detection - making it irreplaceable in legacy automotive and industrial designs requiring direct 8-bit bus interfacing and deterministic CAN 2.0B behavior.
Availability
SJA1000T/N,112 is available at Aetrix Electronics and suitable for automotive body control units, industrial PLC backplanes, off-highway telematics gateways, and medical equipment data buses requiring stable component supply across extended product lifecycles.
Supply support for SJA1000T/N,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications.
The SJA1000T/N,112 belongs to NXP's legacy CAN controller product line, originally developed by Philips Semiconductors to provide robust, pin-compatible upgrades from the PCA82C200 for automotive and industrial network nodes requiring high-integrity serial communication.
FAQ
What is the primary function of the SJA1000T/N,112 in a CAN network?
The SJA1000T/N,112 serves as a stand-alone CAN 2.0B protocol controller that handles message framing, arbitration, error detection/correction, and bit timing - offloading these tasks from the host microcontroller. It manages the complete CAN data link layer, enabling reliable communication between nodes on an industrial or automotive CAN bus. Its dual-mode operation (BasicCAN and PeliCAN) ensures backward compatibility while supporting advanced diagnostics and extended addressing required in modern systems.
Does the SJA1000T/N,112 require an external CAN transceiver?
Yes, the SJA1000T/N,112 requires an external CAN physical-layer transceiver such as the TJA1050 or PCA82C250. It provides differential TX0/TX1 outputs and RX0/RX1 inputs but does not include the voltage-level translation, bus termination, or fault protection needed for direct connection to the CAN bus. The SJA1000T/N,112's OCR register allows configuration of output driver characteristics to match the selected transceiver's input requirements.
How does the SJA1000T/N,112 support both Intel and Motorola microcontroller buses?
The SJA1000T/N,112 supports both bus architectures via the MODE pin: logic high selects Intel mode (using ALE, RD, WR signals), and logic low selects Motorola mode (using AS, E, RD/WR signals). Its multiplexed AD0–AD7 bus, along with configurable control timing in the CDR register, allows seamless integration with 80C51, 68HC11, Z80, and other legacy 8-bit microcontrollers without external bus translators.
What is the significance of the 64-byte RX FIFO in the SJA1000T/N,112?
Unlike earlier CAN controllers with dual 13-byte buffers, the SJA1000T/N,112's 64-byte RX FIFO significantly reduces the risk of message overrun during high-traffic conditions or when the host MCU is delayed by higher-priority interrupts. It allows the CPU to process one received message while up to 64 bytes of additional messages accumulate - improving real-time responsiveness and simplifying firmware design for automotive and industrial applications where deterministic latency is critical.
Can the SJA1000T/N,112 operate without an external crystal?
No, the SJA1000T/N,112 requires an external 24 MHz crystal connected between XTAL1 and XTAL2 pins (with 15 pF load capacitors to VSS1) to drive its internal oscillator. It does not support external clock input or RC-based timing. The CLKOUT pin can be programmed to output a divided version of this clock for synchronizing the host microcontroller, but the crystal remains mandatory for CAN bit timing accuracy and protocol compliance.
SJA1000T/N,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Programmable:
- Not Verified
- Protocol:
- CANbus
- Function:
- Controller
- Interface:
- Parallel
- Standards:
- CAN 2.0
- Voltage - Supply:
- 4.5V ~ 5.5V
- Current - Supply:
- 15mA
- Operating Temperature:
- -40°C ~ 125°C
- Supplier Device Package:
- 28-SO
- Grade:
- -
- Qualification:
- -
SJA1000T/N,112 FAQ
1.How can I place an order for SJA1000T/N,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for SJA1000T/N,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SJA1000T/N,112 reliable?
The price and inventory of SJA1000T/N,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SJA1000T/N,112 is usually 5 days.
3.What payment methods are accepted for SJA1000T/N,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SJA1000T/N,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SJA1000T/N,112?
SJA1000T/N,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SJA1000T/N,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SJA1000T/N,112?
For technical support, including SJA1000T/N,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SJA1000T/N,112 requirements.
6.How does Aetrix verify that SJA1000T/N,112 is sourced from the original manufacturer or authorized distributors?
All SJA1000T/N,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SJA1000T/N,112 meets industry standards.
7.What is the process for return or replacement of SJA1000T/N,112?
All SJA1000T/N,112 units undergo pre-shipment inspection (PSI). If there is an issue with SJA1000T/N,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SJA1000T/N,112 part is unused and in its original packaging.
Return procedure for SJA1000T/N,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SJA1000T/N,112 Tags

-
PTN5150AHXMP
NXP Semiconductors

-
USB3740B-AI9-TR
Microchip Technology

-
USB3740B-AI2-TR
Microchip Technology

-
USB3300-EZK-TR
Microchip Technology

-
USB3300-EZK
Microchip Technology

-
FUSB340TMX
onsemi

-
FUSB302BMPX
onsemi

-
DP83826IRHBR
Texas Instruments

-
MCP2518FDT-E/QBB
Microchip Technology

-
FUSB302MPX
onsemi

-
MCP2518FDT-E/SL
Microchip Technology

-
FT260Q-R
FTDI, Future Technology Devices International Ltd
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

