NXP Semiconductors SJA1105QELY

Overview

SJA1105QELY from NXP Semiconductors is a 5-port automotive Ethernet switch IC supporting configurable 10/100/1000 Mbit/s per port via RGMII/SGMII and 10/100 Mbit/s via MII/RMII, with IEEE 802.1Q VLANs (4096), hardware IEEE 802.1AS timestamping, and AEC-Q100 Grade 2 qualification (-40 °C to +105 °C) for in-vehicle networking.

For engineers reviewing the SJA1105QELY datasheet, SJA1105QELY pinout, SJA1105QELY application, or SJA1105QELY equivalent, key selection considerations include AVB/TSN-ready traffic shaping (16 credit-based shapers), independent I/O voltage domains (1.8/2.5/3.3 V), SPI host interface, LFBGA159 package, and IEEE 1588v2 one-step sync forwarding capability.

Technical Context

The SJA1105QELY implements a store-and-forward switching architecture with per-port MAC-layer configuration, enabling mixed-speed topologies (e.g., RGMII to PHYs, SGMII for cascading). It integrates dedicated hardware accelerators for IEEE 802.1Qav credit-based shaping and IEEE 802.1AS timestamping-both executed without CPU intervention.

Its interface flexibility includes MII/RMII for Fast Ethernet, RGMII with internal delay compensation for Gigabit Ethernet, and SGMII for SerDes links. The device uses a 1.2 V core supply with three independently configurable I/O voltage domains, supporting heterogeneous SoC and PHY interfacing in automotive ECUs.

Key Specifications

Pinout & Package

LFBGA159 (12 mm × 12 mm, 0.8 mm pitch) package with 159 solder balls; thermal pad on underside for enhanced heat dissipation in automotive under-hood environments.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar automotive Ethernet switching applications.

Compared with MARVELL 88Q5152 and TI DP83869HM, the SJA1105QELY uniquely delivers integrated AVB/TSN switching with hardware timestamping, per-port speed configurability, and AEC-Q100 qualification in a single LFBGA159 package-enabling compact, standards-compliant automotive Ethernet nodes without external timing or shaping logic.

Availability

SJA1105QELY is available at Aetrix Electronics and suitable for automotive ADAS domain controllers, IVI head units, zonal gateways, and OTA update hubs requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-compliant performance.

Supply support for SJA1105QELY includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with leadership in automotive Ethernet and secure microcontrollers.

The SJA1105QELY belongs to NXP's SJA1105P/Q/R/S family of automotive-qualified Ethernet switches designed specifically for deterministic in-vehicle networking with AVB/TSN capabilities and functional safety readiness.

FAQ

What Ethernet standards does the SJA1105QELY support?

The SJA1105QELY supports IEEE 802.3 for physical layer compliance, IEEE 802.1Q for VLAN tagging (up to 4096 VLANs), IEEE 802.1AS for hardware timestamping, and IEEE 802.1Qav for credit-based traffic shaping. It also implements IEEE 1588v2 one-step sync forwarding in hardware-enabling precise time synchronization across automotive networks without host CPU involvement. The SJA1105QELY does not support IEEE 802.1Qbu or 802.3br frame preemption.

Does the SJA1105QELY require external PHYs?

The SJA1105QELY operates as a MAC-only switch and requires external PHYs for physical layer connectivity. It supports direct interfacing with 10/100 Mbit/s PHYs via MII/RMII and 10/100/1000 Mbit/s PHYs via RGMII or SGMII. RGMII includes internal delay compensation, eliminating the need for external delay components. The SJA1105QELY itself does not integrate PHY circuitry, so external PHY selection must match the chosen interface mode and data rate.

What is the purpose of the SYNC_OUT pin on the SJA1105QELY?

SYNC_OUT on the SJA1105QELY provides a hardware-synchronized timing signal used to align timestamp domains across multiple cascaded SJA1105QELY devices. This enables deterministic, sub-microsecond time coordination in multi-switch topologies-critical for distributed AVB/TSN applications like sensor fusion or synchronized audio/video playback. The signal is derived from the internal IEEE 802.1AS clock domain and requires no software configuration to activate.

How is configuration loaded into the SJA1105QELY at power-up?

Configuration for the SJA1105QELY is loaded via its quad-wire SPI interface (SPI_CS, SPI_SCK, SPI_MOSI, SPI_MISO) during initialization. A host processor writes a binary configuration table-including port settings, VLAN maps, and traffic shaper parameters-to the switch's internal registers. The SJA1105QELY has no internal non-volatile memory, so configuration must be reloaded after each reset. Boot-time loading is typically handled by the host bootloader or early firmware stage before network stack initialization.

Is the SJA1105QELY pin-compatible with other members of the SJA1105 family?

Yes-the SJA1105QELY is pin-compatible with SJA1105PEL, SJA1105REL, and SJA1105SEL per the ordering information table in the short data sheet, all housed in the LFBGA159 (SOT1427-1) package. This allows hardware reuse across variants differing in feature sets (e.g., AVB support level, number of shapers, or clocking options), provided the PCB layout accommodates the common 159-ball footprint and thermal pad requirements.