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NXP Semiconductors SJA1105TELY
- Part No.:
- SJA1105TELY
- Manufacturer:
- NXP Semiconductors
- Category:
- Controllers
- Package:
- 159-LFBGA
- Datasheet:
-
SJA1105TELY.pdf
- Description:
- IC ETHERNET SWITCH SPI 159LFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:4,834
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Product details
Overview
SJA1105TELY from NXP Semiconductors is a 5-port IEEE 802.3-compliant automotive Ethernet switch supporting MII, RMII, and RGMII per port, with Time-Sensitive Networking (TSN) and Time-Triggered Ethernet (TTEthernet) capabilities, 128 kB frame buffer, and operation from −40 °C to +105 °C for gateway and ECU interconnect applications.
For engineers reviewing the SJA1105TELY datasheet, SJA1105TELY pinout, SJA1105TELY application, or SJA1105TELY equivalent, key selection criteria include deterministic TSN scheduling support, per-port interface configurability (10/100/1000 Mbit/s), IEEE 802.1Qbv time-aware traffic handling, and AEC-Q100 Grade 2 qualification for automotive deployment.
Technical Context
The SJA1105TELY implements a store-and-forward architecture with dedicated hardware blocks for VLAN lookup (4096 VLANs), L2 address learning (1024 entries), ingress policing per priority, and credit-based shapers (10 IEEE 802.1Qav shapers). Its Clock Synchronization Subsystem (CSS) and Schedule Engine (SCH) execute time-triggered message schedules and IEEE 1588v2 one-step sync forwarding.
It integrates Virtual Link Lookup (VL_LU), Virtual Link Policing (VL_POLICE), and Virtual Link Forwarding (VL_FORW) modules to enforce deterministic flow control for up to 1024 time-triggered Ethernet flows, including ingress window checking, active/redundant route management, and per-flow statistics - all operating under AEC-Q100 qualification.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Ports | 5 independent Ethernet ports, each configurable as MII/RMII/RGMII for mixed PHY/host connectivity |
| Data Rates | 10/100 Mbit/s on MII/RMII; 10/100/1000 Mbit/s on RGMII - enables scalable Fast/Gigabit Ethernet integration |
| Frame Buffer | 128 kB on-chip memory - supports bursty traffic buffering without external DRAM |
| TSN Compliance | IEEE 802.1Qbv time-aware traffic shaping and IEEE 802.1Qci per-stream policing - enables hard real-time determinism |
| Operating Temp | −40 °C to +105 °C ambient - meets automotive Grade 2 requirements for under-hood and body domain use |
| Supply Voltage | 1.2 V core (VDD_CORE); 1.8/2.5/3.3 V I/O (VDDIO_HOST/VDDIO_MIIx/VDDIO_CLO) - supports mixed-voltage system interfacing |
| AEC-Q100 | Qualified per AEC-Q100 Rev G - ensures reliability in automotive production environments |
Pinout & Package
LFBGA159 package (12 mm × 12 mm, 0.8 mm pitch) with 159 solder balls; thermal pad exposed on underside for enhanced heat dissipation in automotive PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_CORE (D6, D9, F4, etc.) | Core power supply | 1.2 V supply for internal logic and switching fabric - requires low-noise regulation and local decoupling |
| VDDIO_MIIx (D4, E4, G4, etc.) | I/O supply for xMII interfaces | Configurable 1.8/2.5/3.3 V supply per port group - enables mixed PHY voltage compatibility |
| RST_N (P3) | Active-low reset input | Asynchronous hardware reset; must be held LOW during power-up sequencing before release |
| SCK/SDI/SDO/SS_N (P5, N5, P4, N6) | SPI host interface | 25 MHz max clock; mode 1 (CPOL=0, CPHA=1); used for configuration loading and runtime register access |
| TXC/RXC/TX_CTL/RX_CTL (K14, P10, K13, N12) | RGMII timing and control | Double-data-rate clocking at 125 MHz (1 Gbps); requires matched trace lengths and 1.5–2 ns external delay on clock lines |
| CLK_OUT (H1) | Reference clock output | 25 MHz CMOS output - drives external PHYs or secondary switches in cascaded topologies |
| OSC_IN/OSC_OUT (K2, L1) | Crystal oscillator interface | Supports 25 MHz fundamental-mode crystal; internal load capacitors eliminate need for external caps |
| PTP_CLK (N4) | Precision timestamp clock | Dedicated output for IEEE 1588/802.1AS synchronization - critical for AVB/TSN time-critical applications |
Key Features
| Feature | Design Value |
|---|---|
| Per-port interface flexibility | Each of 5 ports independently set to MII/RMII/RGMII - eliminates need for external level shifters or PHY adapters |
| Hardware TSN acceleration | Integrated VL_LU, VL_POLICE, and VL_FORW blocks - offloads time-triggered scheduling from host CPU and guarantees sub-microsecond latency bounds |
| AVB/TSN coexistence | Simultaneous IEEE 802.1Qav credit-based shaping and IEEE 802.1Qbv time-aware gating - supports mixed criticality traffic (e.g., infotainment + ADAS) |
| Deterministic flow management | 1024 virtual links with per-flow ingress window validation, redundant routing, and statistics - enables safety-critical redundancy in zonal architectures |
| Robust diagnostics | Per-port ingress/egress timestamping, frame mirroring, and broadcast storm protection - simplifies network debugging and fault isolation in vehicle ECUs |
Applications
| Automotive Gateway | ADAS Domain Controller |
|---|---|
Use Scenario: Aggregating CAN FD, LIN, and Ethernet traffic between vehicle domains while enforcing security and QoS policies. IC Role / Device Role / Timing Role: Central Ethernet switch performing VLAN segmentation, rate limiting, and time-synchronized packet forwarding across domains. Use Value: Enables deterministic communication between powertrain and infotainment domains using IEEE 802.1Qbv schedules, reducing software stack complexity and jitter. | Use Scenario: Interconnecting radar, camera, and ultrasonic sensors to a central ADAS processor over deterministic Ethernet. IC Role / Device Role / Timing Role: TSN-aware switch providing hardware-timestamped, time-triggered delivery of sensor frames to meet ISO 26262 ASIL-B timing constraints. Use Value: Guarantees sub-10 µs end-to-end latency for safety-critical sensor fusion data, eliminating reliance on software-based scheduling. |
| Zonal Body Controller | Infotainment Backbone |
Use Scenario: Consolidating door, seat, lighting, and HVAC ECUs into a single zonal controller with unified Ethernet backplane. IC Role / Device Role / Timing Role: Deterministic switch managing scheduled updates for actuator control and unscheduled diagnostics traffic via priority queues. Use Value: Reduces wiring harness weight by replacing point-to-point CAN with daisy-chained Ethernet, while maintaining functional safety via TSN flow policing. | Use Scenario: Bridging audio/video streams between head unit, display, and amplifier using Audio Video Bridging (AVB). IC Role / Device Role / Timing Role: AVB-capable switch implementing IEEE 802.1Qav credit-based shapers and IEEE 802.1AS grandmaster synchronization. Use Value: Delivers jitter-free Class A (≤2 ms) and Class B (≤50 ms) AVB streams without CPU intervention, enabling high-fidelity multi-zone audio. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive Ethernet switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Marvell 88Q5050 | 5-port TSN switch with IEEE 802.1Qbu/802.3br support; no native TTEthernet; larger 169-ball BGA | Targets Ethernet backbone in premium vehicles but lacks time-triggered flow enforcement for ASIL-D systems | Select when prioritizing IEEE 802.1CB frame replication over strict time-triggered scheduling |
| NXP SJA1105P | Pin-compatible variant without TSN/TTEthernet; supports only AVB (802.1Qav/802.1AS); same LFBGA159 package | Suitable for non-safety-critical infotainment networks where deterministic scheduling is not required | Choose for cost-sensitive gateway designs where TSN features are unused and AEC-Q100 Grade 2 suffices |
Compared with Marvell 88Q5050 and NXP SJA1105P, the SJA1105TELY uniquely delivers hardware-enforced time-triggered Ethernet flows with per-link ingress window validation - essential for ISO 26262-compliant zonal controllers requiring guaranteed worst-case latency.
Availability
SJA1105TELY is available at Aetrix Electronics and suitable for automotive gateway, ADAS domain controller, and zonal body controller applications requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-compliant Ethernet switching.
Supply support for SJA1105TELY includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in automotive Ethernet and functional safety.
The SJA1105TELY belongs to NXP's automotive Ethernet switch product line, designed specifically to enable next-generation vehicle architectures with deterministic, time-synchronized communication across safety-critical and infotainment domains.
FAQ
What Ethernet standards does the SJA1105TELY support?
The SJA1105TELY supports IEEE 802.3 for physical layer compliance, IEEE 802.1Q for VLAN tagging, IEEE 802.1Qav for AVB credit-based shaping, IEEE 802.1Qbv for time-aware traffic scheduling, and IEEE 802.1Qci for per-stream policing. It also implements IEEE 1588v2 one-step sync forwarding and IEEE 802.1AS for AVB time synchronization - all verified in the official NXP SJA1105 product data sheet.
Does the SJA1105TELY require external memory for operation?
No, the SJA1105TELY integrates 128 kB of on-chip frame buffer memory and does not require external DRAM or SRAM for standard switching, AVB, or TSN operations. Frame metadata and lookup tables are stored internally, and the Dynamic Memory Management (DMM) block handles allocation and release of memory handles without external dependency.
How is the SJA1105TELY configured during system startup?
The SJA1105TELY is configured via its SPI interface (SCK/SDI/SDO/SS_N) using a binary configuration stream loaded by the host processor after power-up and reset. Configuration includes port interface modes, VLAN settings, TSN schedules, and virtual link definitions. The Configuration Stream Decoder validates CRC before distribution to internal modules - a process documented in the SJA1105 software user manual.
What is the role of the PTP_CLK pin on the SJA1105TELY?
The PTP_CLK pin (N4) outputs a precise 25 MHz clock synchronized to the internal IEEE 1588v2 hardware clock, used to drive external PHYs or timing peripherals requiring traceable PTP reference. This signal enables hardware timestamp alignment across distributed nodes in a TSN network and is distinct from the general-purpose CLK_OUT signal.
Is the SJA1105TELY pin-compatible with other SJA1105 variants?
Yes, the SJA1105TELY is pin-compatible with the SJA1105EL and SJA1105P variants in the same LFBGA159 package. All share identical ball mapping, power domains, and interface pinouts - allowing hardware reuse across AVB-only and TSN-enabled designs, though firmware and configuration differ significantly due to TSN feature enablement.
SJA1105TELY Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 159-LFBGA
- Programmable:
- Not Verified
- Protocol:
- Ethernet
- Function:
- Switch
- Interface:
- SPI
- Standards:
- IEEE 802.3
- Voltage - Supply:
- 1.65V ~ 3.6V
- Current - Supply:
- 3.5mA
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Supplier Device Package:
- 159-LFBGA (12x12)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
SJA1105TELY FAQ
1.How can I place an order for SJA1105TELY through Aetrix?
Please submit a Request for Quotation (RFQ) for SJA1105TELY on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SJA1105TELY reliable?
The price and inventory of SJA1105TELY are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SJA1105TELY is usually 5 days.
3.What payment methods are accepted for SJA1105TELY?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SJA1105TELY transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SJA1105TELY?
SJA1105TELY orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SJA1105TELY order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SJA1105TELY?
For technical support, including SJA1105TELY datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SJA1105TELY requirements.
6.How does Aetrix verify that SJA1105TELY is sourced from the original manufacturer or authorized distributors?
All SJA1105TELY products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SJA1105TELY meets industry standards.
7.What is the process for return or replacement of SJA1105TELY?
All SJA1105TELY units undergo pre-shipment inspection (PSI). If there is an issue with SJA1105TELY, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SJA1105TELY part is unused and in its original packaging.
Return procedure for SJA1105TELY:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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