NXP Semiconductors SLEV610B,699
- Part No.:
- SLEV610B,699
- Manufacturer:
- NXP Semiconductors
- Category:
- RF, RFID, Wireless Evaluation Boards
- Package:
- Datasheet:
-
SLEV610B,699.pdf
- Description:
- EVAL READER BLUEBOARD SLRC610
- Quantity:
- Payment:

- Shipping:

Inventory:1,610
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Product details
Overview
SLEV610B,699 from NXP Semiconductors is a high-performance NFC frontend IC supporting ISO/IEC 15693, ICODE EPC UID, and ISO/IEC 18000-3 Mode 3/EPC Class-1 HF protocols. It operates as a contactless reader/writer with SPI, I²C, and UART host interfaces, integrated 512-byte FIFO, and low-power card detection (LPCD), deployed in industrial access control systems requiring multi-protocol RFID interoperability.
For engineers reviewing the SLEV610B,699 datasheet, SLEV610B,699 pinout, SLEV610B,699 application, or SLEV610B,699 equivalent, key selection considerations include its HVQFN32 package, 27.12 MHz crystal-based PLL clock generation, 3–5.5 V supply range (SLRC61002 variant), 10 Mbit/s SPI speed, and dedicated SAM interface for secure key storage and cryptographic acceleration.
Technical Context
The SLEV610B,699 implements a dual-transmitter analog front-end (TX1/TX2) with RXP/RXN differential receiver inputs and VMID reference, enabling robust 13.56 MHz RF field generation and demodulation. Its digital core integrates a programmable interrupt controller with 16 configurable IRQ sources-including TxIRQ, RxIRQ, LPCDIRQ, and timer underflow events-and five independent timers (Timer0–Timer4), where Timer4 serves as a wakeup timer driven by an internal LFO for low-power card detection.
Host communication is dynamically detected at power-up via IFSEL0/IFSEL1 logic levels, selecting between SPI (MOSI/MISO/SCK/NSS), I²C (SCL/SDA), I²C-L (low-voltage variant), or UART (RX/TX) modes. A separate I²C bus (SCL/SDA pins) connects to a Secure Access Module (SAM), isolating cryptographic operations from the main host interface while supporting high-throughput secure transactions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Protocols | ISO/IEC 15693, ICODE EPC UID, ISO/IEC 18000-3 Mode 3/EPC Class-1 HF - enables interoperability with diverse HF RFID tags across industrial, access, and gaming applications. |
| Host Interfaces | SPI (up to 10 Mbit/s), I²C (Fast mode: 400 kBd; Fast mode plus: 1000 kBd), UART (RS232-level, up to 1228.8 kBd) - provides flexible, high-speed connectivity to microcontrollers without protocol translation overhead. |
| FIFO Buffer | 512-byte depth - absorbs burst data during RF transactions, reducing host polling frequency and improving throughput in high-tag-density environments. |
| Supply Voltage | 3.0 V to 5.5 V (SLRC61002 variant) - supports direct integration into 3.3 V and 5 V industrial control systems without external level shifting. |
| Power-Down Current | 8 nA typical (PDOWN pin HIGH) - enables battery-powered access readers to achieve multi-year standby life with periodic LPCD wakeups. |
| RF Clock Source | Integrated PLL deriving system clock from 27.12 MHz quartz crystal - eliminates need for external clock generator, reducing BOM count and PCB footprint. |
| Operating Temp | −25 °C to +85 °C - qualified for deployment in uncontrolled industrial enclosures and outdoor access terminals. |
Pinout & Package
HVQFN32 (SOT617-1) package: plastic thermal enhanced very thin quad flat package, no leads, 32 terminals + 1 central ground heatsink pad, body size 5 × 5 × 0.85 mm with wettable flanks.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TX1 / TX2 | RF Transmitter Outputs | Deliver modulated 13.56 MHz carrier signals to antenna matching network; dual outputs support balanced or differential antenna configurations. |
| RXP / RXN | Differential RF Receiver Inputs | Accept weak tag response signals with common-mode noise rejection; require external matching network for optimal sensitivity. |
| VDD / PVDD / TVDD / AVDD / DVDD / TVSS / VSS | Power Supply Rails | Separate analog (AVDD), digital (DVDD), transmitter (TVDD), and pad (PVDD) supplies enable noise isolation and optimized power domain management. |
| SCL / SDA | Main I²C Bus | Connect to host MCU for register configuration and command/data exchange; support Fast mode (400 kBd) and Fast mode plus (1000 kBd). |
| IF0–IF3 / IFSEL0 / IFSEL1 | Host Interface Selection | Configure interface mode (SPI/I²C/UART) at power-up via fixed voltage levels; eliminate software initialization dependency for boot-time interface detection. |
| IRQ | Interrupt Request Output | Asserts active-low signal on RF event completion (Tx/Rx), timer expiry, or card detection-enabling event-driven host firmware with minimal polling. |
Key Features
| Feature | Design Value |
|---|---|
| Dedicated SAM I²C Interface | Isolates cryptographic key storage and AES/DES acceleration from main host interface, meeting EAL5+ security requirements for payment-grade access systems. |
| Low-Power Card Detection (LPCD) | Configurable detection threshold and timing via LPCD_OPTIONS register (SLRC61003), enabling <10 μA average current in battery-operated readers with sub-second wake latency. |
| Multi-Protocol RF Frontend | Single hardware platform supports ISO/IEC 15693 inventory, EPC UID read/write, and EPC Class-1 HF commands-reducing SKU count and simplifying certification across global markets. |
| Flexible Antenna Interface | Minimal external components required (typically 4–6 passive parts); supports both series- and parallel-resonant antenna topologies with adjustable load protocol settings. |
| Programmable Timer Unit | Five independent timers (four 16-bit + one LFO-driven wakeup timer) support timeout supervision, watchdog reset, and precise SOF/subcarrier timing alignment per ISO/IEC 15693 physical layer. |
Applications
| Industrial Asset Tracking | Secure Physical Access Control |
|---|---|
Use Scenario: RFID readers embedded in factory floor gateways scan metal-mounted ICODE tags on tools, pallets, and containers moving through production lines. IC Role / Device Role / Timing Role: SLEV610B,699 acts as the contactless protocol engine, handling ASK modulation/demodulation, Manchester decoding, and 1-out-of-4/256 encoding per ISO/IEC 15693, with precise 18.88 µs bit timing. Use Value: Dual TX outputs and differential RX inputs maintain >15 cm read range on metallic surfaces; 512-byte FIFO buffers rapid multi-tag inventories without host bottlenecking. | Use Scenario: Wall-mounted door readers authenticate employees using ICODE EPC UID cards, verifying credentials against a cloud-hosted identity service via secure SAM-assisted AES-128 encryption. IC Role / Device Role / Timing Role: SLEV610B,699 serves as the trusted execution environment's RF interface, routing encrypted challenge-response payloads between SAM and tag via dedicated I²C, with LPCD enabling instant wake-on-card approach. Use Value: Separate SAM I²C bus prevents side-channel leakage; LPCD current of 8 nA in power-down extends battery life to >5 years in wireless locksets. |
| Gaming Token Validation | Automated Library Check-Out |
Use Scenario: Slot machines and arcade cabinets verify proprietary ICODE tokens inserted by players, rejecting counterfeit chips via UID authentication and OTP write-lock enforcement. IC Role / Device Role / Timing Role: SLEV610B,699 executes EPC UID read/write and OTP programming sequences with RTZ encoding at 26.48 kbit/s, enforcing write-protection via hardware fuse control registers. Use Value: Integrated PLL ensures stable 27.12 MHz reference for consistent subcarrier timing; 10 Mbit/s SPI allows real-time token validation within <50 ms per transaction. | Use Scenario: Self-service library kiosks rapidly process stacks of ISO/IEC 15693-tagged books using proximity-based bulk read, with error correction for overlapping tag responses. IC Role / Device Role / Timing Role: SLEV610B,699 performs fast inventory (page read) at 52.96 kbit/s, leveraging Manchester coding and dual subcarrier detection (fc/32, fc/28) per ISO/IEC 15693 Table 7. Use Value: 512-byte FIFO accommodates full 256-tag inventory response; programmable water-level interrupts prevent buffer overflow during high-throughput scanning. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC frontend applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SLRC61003HNE | Wettable flanks HVQFN32 package; supports 2.5–5.5 V supply; enhanced LPCD configuration via LPCD_OPTIONS register and improved load protocol for small antennas. | Better suited for new designs targeting compact form factors and ultra-low-power operation below −40 °C ambient. | Select SLRC61003HNE when designing battery-powered handheld readers or space-constrained access panels requiring extended temperature range (−40 °C to +105 °C). |
| PN5180A0HN/C1 | Single-chip NFC controller (reader + initiator + peer-to-peer); supports ISO/IEC 14443 A/B, FeliCa, and NFC Forum protocols; lacks dedicated SAM interface and LPCD optimization. | Targets smartphone-like NFC functionality (card emulation, P2P) rather than industrial-grade multi-protocol reader applications. | Choose PN5180A0HN/C1 only if ISO/IEC 14443 or NFC Forum compliance is mandatory and SAM-level security is not required. |
Compared with SLRC61003HNE, SLEV610B,699 offers identical core functionality but targets cost-sensitive industrial deployments with standard HVQFN32 packaging and 3–5.5 V operation; versus PN5180A0HN/C1, it delivers superior RF performance and deterministic LPCD for embedded reader systems, albeit without ISO/IEC 14443 support.
Availability
SLEV610B,699 is available at Aetrix Electronics and suitable for industrial asset tracking, secure physical access control, and automated library check-out systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing from authorized NXP channels.
Supply support for SLEV610B,699 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with over 30 years of RFID innovation and leadership in ISO/IEC 15693 and EPC standards.
The SLRC610 product line was designed specifically for high-reliability, multi-protocol HF RFID reader applications demanding low power, robust RF performance, and hardware-accelerated security-targeting industrial automation, physical access, and smart infrastructure markets.
FAQ
What communication protocols does the SLEV610B,699 support?
The SLEV610B,699 supports three distinct HF RFID protocols: ISO/IEC 15693 (including vicinity mode), ICODE EPC UID/OTP, and ISO/IEC 18000-3 Mode 3/EPC Class-1 HF. Each protocol is implemented in hardware with dedicated encoding/decoding logic-1-out-of-4, 1-out-of-256, and Return-to-Zero (RTZ) schemes for ISO/IEC 15693 and EPC UID respectively-and validated per NXP's SLRC610 Rev. 5.1 datasheet. The SLEV610B,699 does not support ISO/IEC 14443 or NFC Forum protocols.
Does the SLEV610B,699 include a built-in oscillator or require an external crystal?
The SLEV610B,699 requires an external 27.12 MHz quartz crystal connected to XTAL1 and XTAL2 pins. It integrates a PLL that derives all internal clocks-including the 13.56 MHz RF carrier-from this crystal, eliminating the need for additional clock generators. This architecture is confirmed in Section 2 Features and benefits ("cost saving by integrated PLL") and Figure 3 block diagram, where "OSC" feeds "PLL" directly. No internal RC oscillator is provided.
What is the purpose of the separate I²C interface on the SLEV610B,699?
The separate I²C interface (SCL/SDA pins) on the SLEV610B,699 is dedicated exclusively to connecting a Secure Access Module (SAM). As stated in Section 1 General description, this interface enables high-security key storage and acts as a "very performant crypto coprocessor." It is electrically and logically isolated from the main host I²C bus, preventing side-channel attacks and ensuring cryptographic operations remain tamper-resistant-critical for access control systems complying with Common Criteria or FIPS 140-2.
How does low-power card detection (LPCD) work on the SLEV610B,699?
LPCD on the SLEV610B,699 operates by periodically energizing the antenna with low-duty-cycle RF bursts and monitoring receiver input (RXP/RXN) for tag-induced loading changes. When a card is detected, the LPCDIRQ interrupt is asserted, waking the host. The feature is enabled via register configuration and consumes only 8 nA in power-down mode (Table 1). While the SLRC61003 variant adds enhanced LPCD_OPTIONS register control, the SLEV610B,699 (SLRC61002) implements baseline LPCD per datasheet Sections 2 and 8.2.1.2.
What host interfaces are supported by the SLEV610B,699 and how are they selected?
The SLEV610B,699 supports SPI (10 Mbit/s), I²C (400/1000 kBd), I²C-L (low-voltage I²C), and UART (RS232-level, up to 1228.8 kBd). Interface selection occurs automatically at power-up or wake-from-power-down by sampling logic levels on IFSEL0, IFSEL1, and multifunction pins IF0–IF3 (Table 9). No software configuration is needed-hardware strapping defines the active interface, ensuring deterministic boot behavior in mission-critical industrial readers.
SLEV610B,699 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Packaging:
- Box
- Product Status:
- Obsolete
- Type:
- RFID Reader
- Frequency:
- 13.56MHz
- Contents:
- Board(s)
- Utilized IC / Part:
- SLRC610
SLEV610B,699 FAQ
1.How can I place an order for SLEV610B,699 through Aetrix?
Please submit a Request for Quotation (RFQ) for SLEV610B,699 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SLEV610B,699 reliable?
The price and inventory of SLEV610B,699 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SLEV610B,699 is usually 5 days.
3.What payment methods are accepted for SLEV610B,699?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SLEV610B,699 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SLEV610B,699?
SLEV610B,699 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SLEV610B,699 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SLEV610B,699?
For technical support, including SLEV610B,699 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SLEV610B,699 requirements.
6.How does Aetrix verify that SLEV610B,699 is sourced from the original manufacturer or authorized distributors?
All SLEV610B,699 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SLEV610B,699 meets industry standards.
7.What is the process for return or replacement of SLEV610B,699?
All SLEV610B,699 units undergo pre-shipment inspection (PSI). If there is an issue with SLEV610B,699, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SLEV610B,699 part is unused and in its original packaging.
Return procedure for SLEV610B,699:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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