Renesas SLG46533M
- Part No.:
- SLG46533M
- Manufacturer:
- Renesas
- Package:
- 22-UFQFN
- Datasheet:
-
SLG46533M.pdf
- Description:
- IC CPLD 26MC 22MSTQFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,103
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SLG46533M from Renesas Electronics is a programmable mixed-signal matrix IC with 22-pin MSTQFN (2 × 2.2 × 0.55 mm, 0.4 mm pitch) packaging, 1.8–5.0 V supply range, -40 °C to +85 °C operating temperature, and integrated I²C interface. It features four analog comparators, two voltage references, 16×8 RAM with OTP-defined initial state, and 26 configurable macrocells including LUTs, DFFs, counters, delays, and deglitch filters - enabling custom logic and signal conditioning in PC peripherals and handheld electronics.
For engineers reviewing the SLG46533M datasheet, SLG46533M pinout, SLG46533M application, or SLG46533M equivalent, this device supports rapid prototyping of glue logic, power sequencing, sensor interface, and I²C-configurable timing functions without FPGA complexity or MCU firmware overhead.
Technical Context
The SLG46533M implements a user-programmable interconnect matrix with OTP NVM configuration, supporting combinational and sequential logic synthesis via macrocell selection (e.g., 2-bit/3-bit/4-bit LUTs, DFFs, CNT/DLY blocks). Its dual-rail power architecture isolates IO groups (0–8 and 9–17), enabling independent drive strength control and current budgeting per side.
It integrates two RC oscillators (25 kHz / 2 MHz / 25 MHz), a crystal oscillator input (XTAL0/XTAL1), analog temperature sensing, and two deglitch filters with edge detection - all configurable via I²C or internal connection matrix. The I²C interface operates at up to 400 kHz with NMOS open-drain SCL/SDA on IO6/IO7 and built-in input filtering.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.8 V (±5 %) to 5.0 V (±10 %): Supports direct interfacing with 1.8 V, 3.3 V, and 5 V logic domains without level shifters. |
| Operating Temperature | -40 °C to +85 °C: Qualified for industrial and consumer embedded applications requiring thermal robustness. |
| I²C Clock Frequency | Up to 400 kHz: Enables standard-mode I²C communication for configuration and status readback. |
| Macrocell Count | 26 configurable macrocells: Includes LUTs (2-/3-/4-bit), DFFs, counters, delays, ACMPs, and filters - sufficient for medium-complexity glue logic. |
| RAM & NVM | 16×8 RAM with OTP-defined initial state: Provides deterministic startup behavior and runtime data storage for state machines. |
| Oscillator Options | Three RC oscillators (25 kHz / 2 MHz / 25 MHz) + crystal input: Offers flexible clock sources for timing-critical and low-power modes. |
| Analog Peripherals | 4 ACMPs, 2 VREFs, 1 temperature sensor: Enables analog threshold detection, reference generation, and thermal monitoring without external components. |
Pinout & Package
SLG46533M uses the 22-pin MSTQFN package (2 mm × 2.2 mm × 0.55 mm, 0.4 mm pitch), optimized for space-constrained PCB layouts. Pin functions are fully configurable via OTP programming, with dedicated I²C (IO6/SCL, IO7/SDA), crystal (IO13/XTAL0, IO14/XTAL1), and analog inputs (ACMPx±, VREF0).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IO0 | General-purpose input | Digital input without Schmitt trigger; no output capability - used for fixed-sense control signals. |
| IO1, IO3, IO5, IO8, IO10, IO11, IO13, IO15, IO16 | GPIO with OE* | Configurable bidirectional I/O; OE signal routed internally allows software-controlled direction switching. |
| IO2, IO4, IO6, IO7, IO9, IO12, IO14, IO17 | General-purpose I/O | Supports push-pull (1x/2x), open-drain NMOS (1x/2x/4x), or PMOS outputs - suitable for I²C, reset signaling, or LED drive. |
| IO6 / IO7 | I²C SCL / SDA | Hardwired open-drain NMOS outputs only in I²C mode; require external pull-ups and comply with 400 kHz timing specs. |
| IO13 / IO14 | XTAL0 / XTAL1 | Dedicated crystal oscillator inputs; support external 1–24 MHz crystals for precise timing or clock recovery. |
| IO15 / IO16 | VREF0 output | Programmable voltage reference output (typically ~1.2 V); usable as ACMP reference or analog subsystem bias. |
Key Features
| Feature | Design Value |
|---|---|
| Read Back Protection (Read Lock) | Prevents unauthorized extraction of OTP configuration, securing proprietary logic design against reverse engineering. |
| Two-Rail Power Architecture | Separates IO groups (0–8 and 9–17) for independent current budgeting - simplifies thermal management and avoids cross-rail noise coupling. |
| Deglitch Filters with Edge Detection | Two dedicated filter macrocells suppress sub-35 ns glitches (at 5 V) and generate clean edge pulses for interrupt generation or debouncing. |
| Configurable Oscillator Selection | User-selectable 25 kHz / 2 MHz / 25 MHz RC oscillators or external crystal - enables dynamic trade-offs between accuracy, power, and startup time. |
| I²C Slave Interface | Full I²C protocol compliance (400 kHz max) with addressable register map - allows real-time reconfiguration and status monitoring in-system. |
| OTP Memory with Defined Initial State | 16×8 RAM initialized from OTP at power-on - ensures deterministic behavior before user firmware or host controller intervention. |
Applications
| Power Sequencing Control | USB-C Port Manager Logic |
|---|---|
|
Use Scenario: Coordinating multi-rail power-up/down sequences in laptops and docking stations to meet Intel VRD or USB PD specifications. IC Role / Device Role / Timing Role: Configurable delay chains, voltage monitors (ACMPs), and state machines replace discrete timers and comparators. Use Value: Reduces BOM count by 6+ components while enabling field-updatable sequencing logic via I²C. |
Use Scenario: Managing CC line detection, VCONN enable/disable, and role swap handshaking in USB-C receptacles. IC Role / Device Role / Timing Role: ACMPs monitor CC voltage levels; LUTs implement PD message parsing logic; deglitch filters suppress connector bounce. Use Value: Eliminates need for dedicated USB-C controller IC in cost-sensitive accessories and embedded hosts. |
| Industrial Sensor Signal Conditioning | PC Peripheral Status Monitoring |
|
Use Scenario: Converting analog sensor outputs (e.g., thermistor, pressure transducer) into digital alerts or PWM fan control signals. IC Role / Device Role / Timing Role: ACMPs compare sensor voltage to VREF0; counters generate variable-duty-cycle PWM; temperature sensor provides self-calibration reference. Use Value: Achieves <1% threshold accuracy over -40 °C to +85 °C without external precision references or op-amps. |
Use Scenario: Detecting hot-plug events, button presses, and LED status feedback in keyboards, mice, and docking stations. IC Role / Device Role / Timing Role: Schmitt-trigger inputs debounce mechanical switches; edge-detect filters generate clean interrupts; GPIOs drive status LEDs with programmable blink patterns. Use Value: Enables zero-firmware peripheral designs with full configurability via host I²C writes during manufacturing test. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable mixed-signal logic applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SLG46537V | 20-pin STQFN package; identical macrocell count and feature set but lacks IO15/IO16 VREF0 outputs and IO17 EXT_CLK2 input. | Better suited for space-constrained designs where VREF routing or third external clock input is unnecessary. | Select SLG46537V when board layout prioritizes smallest footprint and VREF0 duplication or triple clock input is not required. |
| SLG46620V | Higher macrocell count (32 vs. 26), added 10-bit ADC, and enhanced I²C slave addressing - but requires 24-pin QFN and higher VDD minimum (2.3 V). | Targeted at designs needing analog-to-digital conversion or deeper state-machine depth beyond SLG46533M's capacity. | Choose SLG46620V only if ADC integration or >26 macrocells are mandatory; not drop-in compatible due to pin count and supply constraints. |
Compared with SLG46533M, SLG46537V offers identical functionality in a smaller 20-pin package but omits two VREF outputs and one external clock input, while SLG46620V adds ADC and macrocells at the cost of larger size and higher minimum supply voltage - making SLG46533M the optimal balance of analog integration, I/O flexibility, and compact packaging for mid-complexity mixed-signal tasks.
Availability
SLG46533M is available at Aetrix Electronics and suitable for PC peripheral design, USB-C accessory development, industrial sensor interface, and handheld electronics requiring stable component supply across production lifecycles.
Supply support for SLG46533M includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The GreenPAK family, including SLG46533M, is designed for rapid implementation of custom mixed-signal logic in cost-sensitive, space-constrained applications - replacing discrete glue logic and reducing firmware dependency.
FAQ
What is the primary function of the SLG46533M in system design?
The SLG46533M serves as a field-configurable mixed-signal logic device that replaces discrete comparators, timers, latches, and level translators. Its OTP-programmable macrocells allow engineers to implement custom power sequencing, sensor interface, I²C-based control logic, and glitch-filtered event detection - all within a single 22-pin MSTQFN package. SLG46533M eliminates the need for multiple passive and active components while enabling post-manufacturing updates via I²C.
Does the SLG46533M support both 1.8 V and 5 V logic interfaces simultaneously?
Yes, SLG46533M operates across a 1.8 V (±5 %) to 5.0 V (±10 %) supply range and supports mixed-voltage I/O. Input thresholds scale with VDD (e.g., VIH = 1.06 V at 1.8 V, 2.68 V at 5 V), and output drive strength is specified per supply level. However, all pins share the same VDD rail - true dual-supply operation (e.g., 1.8 V core + 5 V I/O) is not supported. SLG46533M must be powered from a single supply matching the dominant logic domain.
How is the SLG46533M programmed, and is the configuration retained after power loss?
The SLG46533M is programmed once using Renesas' GreenPAK Designer software and a compatible programmer (e.g., SLG4DVKHV). Configuration data is stored in one-time-programmable (OTP) non-volatile memory, ensuring permanent retention without battery backup or external EEPROM. After programming, the SLG46533M powers up with fully functional logic - no boot code or host initialization is required. Read Lock protection prevents unauthorized readout of the OTP contents.
Can the SLG46533M replace a microcontroller in simple control tasks?
SLG46533M is not a microcontroller and lacks program memory, ALU, or instruction execution. However, for deterministic, low-latency, combinatorial or finite-state logic (e.g., power sequencing, switch debouncing, PWM generation, or I²C register mapping), SLG46533M often outperforms MCUs in speed (<15 ns propagation delay), power (<1 µA quiescent at 1.8 V), and reliability (no firmware crashes or watchdog resets). SLG46533M complements MCUs by offloading fixed-function tasks, freeing CPU resources - it does not replace them in programmable algorithmic applications.
What are the key timing limitations when using the SLG46533M's internal oscillators?
The SLG46533M's RC oscillators exhibit frequency variation: ±8.72 % over -40 °C to +85 °C at 5 V for the 25 kHz oscillator, and ±15.23 % for the 2 MHz oscillator. Startup time ranges from 0.01 µs (25 MHz fast start) to 2.03 ms (1.8 V power-on). For timing-critical functions like UART baud generation or precise PWM, use the crystal oscillator input (IO13/IO14) instead - SLG46533M supports external crystals up to 24 MHz with ppm-level stability. Internal RC sources are best suited for non-critical clocks, wake-up timers, or coarse delays.
SLG46533M Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 22-UFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Programmable Type:
- OTP
- Delay Time tpd(1) Max:
- -
- Voltage Supply - Internal:
- 1.71V ~ 1.89V, 3V ~ 3.6V, 4.5V ~ 5.5V
- Number of Logic Elements/Blocks:
- -
- Number of Macrocells:
- 26
- Number of Gates:
- -
- Number of I/O:
- 17
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 22-MSTQFN (2x2.2)
SLG46533M FAQ
1.How can I place an order for SLG46533M through Aetrix?
Please submit a Request for Quotation (RFQ) for SLG46533M on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SLG46533M reliable?
The price and inventory of SLG46533M are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SLG46533M is usually 5 days.
3.What payment methods are accepted for SLG46533M?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SLG46533M transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SLG46533M?
SLG46533M orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SLG46533M order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SLG46533M?
For technical support, including SLG46533M datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SLG46533M requirements.
6.How does Aetrix verify that SLG46533M is sourced from the original manufacturer or authorized distributors?
All SLG46533M products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SLG46533M meets industry standards.
7.What is the process for return or replacement of SLG46533M?
All SLG46533M units undergo pre-shipment inspection (PSI). If there is an issue with SLG46533M, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SLG46533M part is unused and in its original packaging.
Return procedure for SLG46533M:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SLG46533M Tags

-
5M40ZE64C5N
Intel

-
ATF1502ASV-15AU44
Microchip Technology

-
5M80ZE64C5N
Intel

-
5M80ZT100C5N
Intel

-
ATF1502AS-10AU44
Microchip Technology

-
ATF1502AS-10JU44
Microchip Technology

-
5M80ZE64I5N
Intel

-
5M80ZT100I5N
Intel
-
LC4032V-75TN48C
Lattice Semiconductor Corporation

-
ATF1504ASV-15AU44
Microchip Technology

-
ATF1504AS-10JU44
Microchip Technology

-
5M160ZE64C5N
Intel
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

