Renesas SLG59M611V
- Part No.:
- SLG59M611V
- Manufacturer:
- Renesas
- Package:
- 8-PowerWFDFN
- Datasheet:
-
SLG59M611V.pdf
- Description:
- IC PWR SWITCH N-CHAN 1:1 8TDFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,580
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Product details
Overview
SLG59M611V from Renesas is a single-channel, N-channel high-side load switch optimized for 2.5 V to 5.5 V input rails, delivering 4 A continuous output current with 22 mΩ typical RDS(ON) at VIN = 5 V and TA = 25 °C. It integrates reverse-current blocking, adjustable inrush control, thermal shutdown, and overcurrent protection - designed for compact power rail switching in portable computing and enterprise peripherals.
For engineers reviewing the SLG59M611V datasheet, SLG59M611V pinout, SLG59M611V application, or SLG59M611V equivalent, key selection criteria include its 22 mΩ RDS(ON), -40 °C to +85 °C industrial temperature range, TDFN-8 (1.5 × 2.0 mm) package, and integrated ACL/SCL/TSD/RCB protection features - all critical for reliable high-density power sequencing.
Technical Context
The SLG59M611V employs an integrated charge pump to drive the N-channel MOSFET gate above VIN, enabling low RDS(ON) without external bias. Its slew rate is capacitor-adjustable via the RAMP pin, allowing controlled VOUT ramp-up to limit inrush current during hot-swap events.
Reverse-current blocking is implemented using back-to-back FET architecture, preventing VOUT from feeding back into VIN when disabled. Protection logic includes fixed short-circuit current limit (SCL), resistor-adjustable active current limit (ACL), and auto-restart thermal shutdown (TSD) - all operating independently of external microcontroller supervision.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Continuous IOUT | 4 A - supports USB-powered peripherals and PCIe add-in card auxiliary rails without derating at 85 °C ambient. |
| RDS(ON) (typ) | 22 mΩ at VIN = 5 V - enables <100 mV dropout at 4.5 A, minimizing power loss and self-heating in space-constrained layouts. |
| VIN Range | 2.5 V to 5.5 V - compatible with single-cell Li-ion (3.0–4.2 V), 3.3 V logic rails, and 5 V USB PD sink applications. |
| Operating Temp | -40 °C to +85 °C - qualified for industrial-grade embedded systems including multifunction printers and network edge devices. |
| Protection Features | ACL (resistor-adjustable), SCL (fixed), TSD (auto-restart), RCB (back-to-back FET) - eliminates need for discrete current-sense amplifiers or external blocking diodes. |
| Output Discharge | Integrated VOUT discharge circuit - ensures rapid VOUT decay (<1 ms) after disable, preventing floating nodes in multi-rail power domains. |
| Package | TDFN-8 (1.5 × 2.0 mm, 0.5 mm pitch) - 3 mm² footprint with exposed thermal pad for ≤45 °C/W θJA in 2-layer PCBs. |
Pinout & Package
TDFN-8 (1.5 mm × 2.0 mm, 0.5 mm pitch) with exposed thermal pad (Pin 5). RoHS-compliant, halogen-free, moisture sensitivity level 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (IN) | Input Power Rail | Primary high-side power input (2.5–5.5 V); connects directly to source of internal N-FET. |
| 2 (EN) | Active-High Enable | Logic-level control (1.2 V min high threshold); internal pull-down ensures default OFF state at power-up. |
| 3 (OUT) | Switched Output | Drives load; internally connected to drain of main N-FET; supports reverse-current blocking when disabled. |
| 4 (RAMP) | Inrush Control Input | Capacitor-connected node setting VOUT slew rate; 1 nF yields ~1.5 ms rise time from 10% to 90%. |
| 5 (GND) | Power & Signal Ground | Common reference for all internal circuits; must be tied to exposed thermal pad for optimal thermal performance. |
| 6 (FLAG) | Fault Indicator Output | Open-drain output pulled low during overcurrent, thermal shutdown, or undervoltage lockout (UVLO). |
| 7 (VDD) | Charge Pump Supply | Internal charge pump supply; bypassed externally with 100 nF ceramic capacitor to GND. |
| 8 (ACL) | Adjustable Current Limit | Resistor-connected node setting active current limit threshold from 1.5 A to 6 A (100 kΩ → 1.5 A; 10 kΩ → 6 A). |
Key Features
| Feature | Design Value |
|---|---|
| Reverse-current blocking | Back-to-back FET architecture prevents VOUT → VIN conduction when EN = low, eliminating need for external Schottky diode. |
| Adjustable inrush control | RAMP pin accepts external capacitor (0.1–10 nF) to set VOUT rise time from 0.5 ms to >10 ms, suppressing peak inrush currents in capacitive loads. |
| Resistor-programmable current limit | ACL pin supports 1.5–6 A active current limit via single external resistor - enables precise fault margining without firmware intervention. |
| Integrated thermal shutdown | Auto-restart TSD triggers at 150 °C junction temperature and resumes operation once TJ drops below 135 °C, ensuring safe recovery after overload. |
| VOUT discharge circuit | Internal 120 Ω NMOS switch discharges VOUT to GND within 1 ms after EN deactivation, preventing unintended wake-up in sleep-mode systems. |
Applications
| USB-C Peripheral Power Switching | Enterprise Printer Power Sequencing |
|---|---|
|
Use Scenario: Switching 5 V power to USB-C downstream ports in docking stations with hot-plug detection and inrush suppression. IC Role / Device Role / Timing Role: High-side load switch controlling VBUS delivery while enforcing strict inrush limits and reverse-current isolation. Use Value: Eliminates discrete MOSFET + driver + sense resistor BOM; 22 mΩ RDS(ON) reduces power loss by 40% vs. comparable 35 mΩ alternatives at 3 A. |
Use Scenario: Independent power control for scanner, print engine, and paper feed subsystems in multifunction copiers. IC Role / Device Role / Timing Role: Industrial-grade load switch enabling staggered power-up and fault-isolated shutdown per module. Use Value: -40 °C to +85 °C rating ensures reliability across office environments; FLAG output feeds directly to system MCU for real-time fault logging. |
| Notebook Subsystem Power Management | PCIe Add-in Card Auxiliary Rail Control |
|
Use Scenario: Enabling/disabling 3.3 V or 5 V rails for SSD, WWAN, or Thunderbolt controllers during OS suspend/resume cycles. IC Role / Device Role / Timing Role: Low-quiescent-load switch with fast turn-on (<10 µs) and controlled slew to meet ACPI power-state transition timing. Use Value: Integrated VOUT discharge guarantees clean rail collapse before entering S3/S4 states, avoiding latch-up in companion ICs. |
Use Scenario: Controlling +12 V or +3.3 V auxiliary power to PCIe riser cards in servers and workstations with hot-swap capability. IC Role / Device Role / Timing Role: High-current (4 A) load switch with SCL/ACL protection to prevent bus faults during insertion/removal. Use Value: 22 mΩ RDS(ON) limits voltage drop to <88 mV at full load, maintaining PCIe specification compliance on VADJ rails. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-side load switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SLG59M610V | Identical RDS(ON) (22 mΩ), same TDFN-8 package, but rated for 4 A max (same as SLG59M611V) and shares identical ACL/SCL/TSD/RCB feature set. | No functional difference in protection or control; differs only in factory-programmed default ACL threshold (SLG59M610V fixed at 6 A, SLG59M611V adjustable 1.5–6 A). | Select SLG59M611V when programmable current limit is required; SLG59M610V suits fixed-threshold designs needing simpler BOM. |
| SLG59M1496V | Same 4 A rating and TDFN-8 package, but higher RDS(ON) (7.8 mΩ), no reverse-current blocking, and lacks FLAG output - uses open-drain FAULT instead. | Targeted at cost-sensitive applications where RCB is unnecessary and lower conduction loss justifies larger die size; not suitable for bidirectional isolation use cases. | Choose SLG59M1496V only if RDS(ON) < 10 mΩ is mandatory and reverse-current blocking is omitted from system requirements. |
Compared with SLG59M610V, SLG59M611V offers field-adjustable current limiting versus fixed threshold; compared with SLG59M1496V, it adds robust reverse-current blocking and a dedicated FLAG signal - making SLG59M611V the preferred choice for USB-C and enterprise peripheral designs requiring full fault visibility and bidirectional isolation.
Availability
SLG59M611V is available at Aetrix Electronics and suitable for notebook subsystem power management, enterprise printer power sequencing, and USB-C peripheral switching requiring stable component supply and industrial-temperature qualification.
Supply support for SLG59M611V includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded design innovation for automotive, industrial, infrastructure, and IoT applications.
The GreenFET family, including SLG59M611V, was engineered specifically for high-efficiency, space-constrained high-side power rail control - emphasizing ultra-low RDS(ON), integrated protection, and minimal PCB footprint across consumer and industrial markets.
FAQ
What is the maximum continuous output current supported by the SLG59M611V?
The SLG59M611V supports 4 A continuous output current across its full operating temperature range (-40 °C to +85 °C) with proper PCB thermal design. Derating is not required up to 85 °C ambient when mounted on a 2-layer board with 1 in² copper pour connected to the exposed thermal pad (Pin 5). At 4 A and 5 V input, conduction loss remains under 350 mW due to its 22 mΩ RDS(ON).
Does the SLG59M611V provide reverse-current blocking, and how is it implemented?
Yes, the SLG59M611V provides true reverse-current blocking using an internal back-to-back N-channel FET configuration. When the device is disabled (EN = low), both FETs are turned off, preventing current flow from VOUT back to VIN. This eliminates the need for external blocking diodes in applications such as USB-C power delivery sinks or battery-backed subsystems where backfeed could damage upstream sources.
How is the current limit threshold configured on the SLG59M611V?
The SLG59M611V implements resistor-adjustable active current limiting via the ACL pin. A single external resistor between ACL and GND sets the current limit threshold from 1.5 A to 6 A - for example, 100 kΩ yields 1.5 A, while 10 kΩ yields 6 A. This allows precise matching to load requirements without firmware or external sensing circuitry, and operates independently of the fixed short-circuit limit (SCL) that triggers faster during hard faults.
What is the function of the FLAG pin on the SLG59M611V?
FLAG is an open-drain fault indicator pin on the SLG59M611V that pulls low during any fault condition: overcurrent (ACL or SCL event), thermal shutdown (TSD), or input undervoltage lockout (UVLO). It remains high during normal operation and provides immediate, hardware-level fault signaling to the host MCU without requiring polling or ADC reads - enabling deterministic system-level error handling in real-time applications like printers or docking stations.
Can the SLG59M611V operate with a 3.3 V input supply, and what is its minimum input voltage?
Yes, the SLG59M611V operates with a 3.3 V input supply and supports a minimum input voltage of 2.5 V. Its integrated charge pump ensures sufficient gate drive for the main N-FET down to 2.5 V, maintaining 22 mΩ RDS(ON) performance across the full 2.5–5.5 V range. This makes SLG59M611V suitable for single-cell Li-ion (2.7–4.2 V) and 3.3 V logic rail applications without external boost circuitry.
SLG59M611V Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 8-PowerWFDFN
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Switch Type:
- General Purpose
- Number of Outputs:
- 1
- Ratio - Input:Output:
- 1:1
- Output Configuration:
- High Side
- Output Type:
- N-Channel
- Interface:
- -
- Voltage - Load:
- -
- Voltage - Supply (Vcc/Vdd):
- 2.5V ~ 5.5V
- Current - Output (Max):
- 4A
- Rds On (Typ):
- 22mOhm
- Input Type:
- CMOS
- Features:
- -
- Fault Protection:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-FC-TDFN (1.5x2)
SLG59M611V FAQ
1.How can I place an order for SLG59M611V through Aetrix?
Please submit a Request for Quotation (RFQ) for SLG59M611V on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SLG59M611V reliable?
The price and inventory of SLG59M611V are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SLG59M611V is usually 5 days.
3.What payment methods are accepted for SLG59M611V?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SLG59M611V transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SLG59M611V?
SLG59M611V orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SLG59M611V order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SLG59M611V?
For technical support, including SLG59M611V datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SLG59M611V requirements.
6.How does Aetrix verify that SLG59M611V is sourced from the original manufacturer or authorized distributors?
All SLG59M611V products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SLG59M611V meets industry standards.
7.What is the process for return or replacement of SLG59M611V?
All SLG59M611V units undergo pre-shipment inspection (PSI). If there is an issue with SLG59M611V, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SLG59M611V part is unused and in its original packaging.
Return procedure for SLG59M611V:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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