Texas Instruments SM320C6701GLPW14
- Part No.:
- SM320C6701GLPW14
- Manufacturer:
- Texas Instruments
- Category:
- DSP (Digital Signal Processors)
- Package:
- 429-BCBGA, FCBGA
- Datasheet:
-
SM320C6701GLPW14.pdf
- Description:
- SINGLE CORE C67X FLOATING-POINT
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SM320C6701GLPW14 from Texas Instruments is a radiation-tolerant, high-performance floating-point digital signal processor (DSP) based on the VelociTI VLIW architecture. It delivers up to 1 GFLOPS at 167 MHz, features eight 32-bit functional units (four ALUs, two multipliers), 1 M-bit on-chip SRAM (512K-bit program/cache + 512K-bit dual-access data), and supports IEEE single- and double-precision arithmetic - deployed in radar signal processing, avionics flight control, and satellite telemetry systems.
For engineers reviewing the SM320C6701GLPW14 datasheet, SM320C6701GLPW14 pinout, SM320C6701GLPW14 application, or SM320C6701GLPW14 equivalent, key selection criteria include its 429-pin ceramic BGA package, 1.9-V core / 3.3-V I/O supply scheme, MIL-PRF-38535 QML qualification, extended −55°C to 115°C operating range, and glueless EMIF support for SDRAM, SBSRAM, and asynchronous memory.
Technical Context
The SM320C6701GLPW14 implements a dual-path VelociTI VLIW CPU with two register files (A/B, 16×32-bit each) and eight functional units: .L1/.S1/.M1/.D1 (Side A) and .D2/.M2/.S2/.L2 (Side B), six of which execute floating-point instructions. Its load-store architecture enables byte-, half-word-, and word-addressable memory access with full conditional execution and instruction packing.
It integrates a flexible PLL clock generator (x1/x4 modes), IEEE-1149.1 JTAG boundary-scan, four-channel bootloading, 16-bit HPI with full memory map access, two McBSPs supporting T1/E1, AC97, and SPI protocols, and two 32-bit general-purpose timers - all synchronized to a single 256-bit-wide fetch packet delivering up to eight 32-bit instructions per cycle.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | VelociTI advanced VLIW with 8 independent functional units and dual-register-file load-store design |
| Performance | 1 GFLOPS at 167 MHz; 334 MMACS via dual MAC capability per cycle |
| On-Chip Memory | 512 K-bit program/cache (64K bytes) + 512 K-bit dual-access data RAM (64K bytes) |
| EMIF Support | Glueless interface to SDRAM, SBSRAM, SRAM, and EPROM with 32-bit data bus and 22-bit address bus |
| Supply Voltages | 1.9 V core (CVDD) and 3.3 V I/O (DVDD) - separate power domains with dedicated analog PLL pins (PLLV/PLLG/PLLF) |
| Operating Range | −55°C to +115°C (extended W grade), qualified per MIL-PRF-38535 Class V |
| Package | 429-pin ceramic ball grid array (CBGA), 27 mm × 27 mm, GLP suffix |
Pinout & Package
SM320C6701GLPW14 uses a 429-pin ceramic BGA (GLP package), 27 mm × 27 mm footprint, with 1.27-mm ball pitch. Power and ground pins are distributed across multiple corners and center rows to minimize noise and ensure stable core/I/O rail decoupling under high-speed switching conditions.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKIN (A14) | Clock Input | Primary oscillator input driving internal PLL; supports external crystal or clock source |
| CLKOUT1 (Y6) | Clock Output | Full-speed device clock output (167 MHz); used for synchronizing external peripherals |
| HPI Data Bus HD[15:0] (D11–C7) | Host Port Interface | 16-bit bidirectional data path enabling host CPU access to full internal memory map |
| EMIF Address EA[21:2] (L4–P6) | External Memory Interface | 20-bit address bus supporting up to 4 MB of external memory space |
| EMIF Data ED[31:0] (U18–W9) | External Memory Interface | 32-bit bidirectional data bus with BE[3:0] byte enables for precise memory access control |
| McBSP0 Signals (J21, M21, K20, L21, N16, P16) | Multichannel Serial Port | Full-duplex synchronous serial interface supporting T1/E1 framing, AC97, and SPI protocols |
| CVDD (G13, E10, AA11, etc.) | Core Supply | 1.9-V analog/digital core power - requires low-noise regulation and local decoupling |
| DVDD (J19, J3, N19, etc.) | I/O Supply | 3.3-V I/O power domain - independent from core supply to support mixed-voltage system interfacing |
Key Features
| Feature | Design Value |
|---|---|
| IEEE Floating-Point Compliance | Hardware-accelerated single- and double-precision arithmetic meeting IEEE 754 standards |
| Instruction Packing | Variable-length execute packets reduce code size by eliminating NOP padding in VLIW instruction streams |
| Conditional Execution | All instructions support condition codes - eliminates branch penalties and improves pipeline efficiency |
| Memory Protection | 8-bit overflow protection and saturation logic prevent arithmetic wraparound in real-time control loops |
| Boot Flexibility | Four-channel bootloading from HPI, EMIF, McBSP, or internal ROM enables field-upgradable firmware deployment |
Applications
| Radar Signal Processing | Avionics Flight Control |
|---|---|
Use Scenario: Real-time pulse-Doppler processing of phased-array radar returns with adaptive beamforming and clutter suppression. IC Role / Device Role / Timing Role: Primary floating-point compute engine executing FFTs, matrix inversions, and Kalman filters at deterministic latency. Use Value: 1 GFLOPS throughput and dual-MAC capability enable sub-millisecond response for threat detection and tracking loops. |
Use Scenario: Closed-loop control of fly-by-wire actuators using sensor fusion from inertial measurement units and air data computers. IC Role / Device Role / Timing Role: Safety-critical DSP managing PID controllers, fault detection, and redundancy arbitration in DO-254-compliant hardware. Use Value: MIL-PRF-38535 Class V qualification and −55°C to 115°C operation ensure reliability in high-vibration, wide-temperature aircraft environments. |
| Satellite Telemetry Processing | Military Communications Crypto |
Use Scenario: Onboard demodulation, decoding, and error correction of downlinked telemetry streams from LEO satellites. IC Role / Device Role / Timing Role: Dedicated baseband processor handling convolutional/Viterbi decoding, Reed-Solomon correction, and frame synchronization. Use Value: Dual McBSPs with AC97 and T1/E1 framing support direct interface to RF front-end ASICs without glue logic. |
Use Scenario: Embedded cryptographic acceleration for secure voice/data links in tactical radios and SATCOM terminals. IC Role / Device Role / Timing Role: Offloading AES, SHA, and elliptic-curve operations from host microcontroller while maintaining side-channel resistance. Use Value: 32 general-purpose registers and bit-field manipulation instructions accelerate modular arithmetic and constant-time crypto primitives. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar floating-point DSP applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SM320C6713BGLP | Higher clock rate (225 MHz), larger on-chip memory (256K words RAM), enhanced DMA controller, but non-radiation-hardened | Targeted at commercial/industrial embedded systems requiring higher throughput but not space-grade reliability | Select when radiation tolerance is unnecessary and cost/performance favors newer C6713B silicon |
| TMS320C6748BZWT | ARM Cortex-A8 + C67x DSP dual-core, 32KB L1/L2 cache, integrated DDR2 controller, 1.0 GHz max, but no MIL-spec qualification | Designed for Linux-capable multimedia and industrial HMI platforms with rich peripheral integration | Choose for applications needing OS support, GUI rendering, or heterogeneous processing - not for radiation-hardened environments |
Compared with SM320C6701GLPW14, the SM320C6713BGLP offers higher computational density but lacks QML qualification, while the TMS320C6748BZWT provides modern SoC features and software ecosystem support at the expense of radiation hardness and deterministic real-time behavior.
Availability
SM320C6701GLPW14 is available at Aetrix Electronics and suitable for radar signal processing, avionics flight control, and satellite telemetry systems requiring stable component supply across long-lifecycle defense and aerospace programs.
Supply support for SM320C6701GLPW14 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and digital signal technologies, with decades of heritage in high-reliability aerospace and defense components.
The SM320C6701GLPW14 belongs to TI's military-grade C67x DSP family, engineered specifically for radiation-tolerant, high-throughput floating-point computation in mission-critical embedded systems where deterministic timing and environmental resilience are mandatory.
FAQ
What is the operating temperature range for the SM320C6701GLPW14?
The SM320C6701GLPW14 is rated for an extended industrial/military temperature range of −55°C to +115°C (W grade), verified per MIL-PRF-38535 Class V requirements. This specification ensures reliable operation in harsh environments such as airborne radar housings, satellite payload bays, and missile guidance sections where thermal cycling and extreme ambient conditions are routine. The SM320C6701GLPW14 maintains full functional performance across this entire range without derating.
Does the SM320C6701GLPW14 support IEEE 754 double-precision arithmetic?
Yes, the SM320C6701GLPW14 includes dedicated hardware support for IEEE 754 double-precision floating-point instructions executed by six of its eight functional units (.L1, .M1, .D1, .D2, .M2, .L2). This enables high-accuracy numerical computation required in orbital mechanics solvers, precision navigation algorithms, and scientific signal modeling - all without software emulation overhead. The SM320C6701GLPW14 guarantees full compliance with IEEE 754 rounding and exception-handling semantics.
How many external memory interfaces does the SM320C6701GLPW14 provide?
The SM320C6701GLPW14 integrates a single 32-bit External Memory Interface (EMIF) supporting glueless connection to SDRAM, SBSRAM, SRAM, and EPROM devices. It provides CE[3:0], BE[3:0], EA[21:2], and ED[31:0] signals plus dedicated control lines for SDRAM (SDRAS/SDCAS/SDWE/SDCLK) and SBSRAM (SSADS/SSOE/SSWE/SSCLK). The SM320C6701GLPW14 does not include multiple independent EMIFs - all external memory accesses route through this unified interface.
Is the SM320C6701GLPW14 pin-compatible with fixed-point C62x devices?
Yes, the SM320C6701GLPW14 is explicitly designed to be pin-compatible with the SMJ320C6201 fixed-point DSP, sharing identical package dimensions, ball layout, and signal mapping for power, ground, clock, reset, and major peripheral interfaces. This allows drop-in replacement in legacy C6201-based designs when floating-point capability is needed - though software recompilation and memory remapping are required due to architectural differences. The SM320C6701GLPW14 retains backward compatibility at the PCB level.
What development tools are officially supported for the SM320C6701GLPW14?
Texas Instruments officially supports the SM320C6701GLPW14 with the XDS510 JTAG emulator (TMDS00510), C6000 Code Generation Tools (C compiler, assembler, linker), C6000 DSP/BIOS real-time kernel, and the TMDX3260A6201 evaluation module. These tools enable full-cycle development including cycle-accurate simulation, hardware-in-the-loop debugging, and real-time profiling. The SM320C6701GLPW14 is not supported by newer C6000 IDE versions targeting C674x or C66x families - legacy toolchains remain the validated path.
SM320C6701GLPW14 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 429-BCBGA, FCBGA
- Packaging:
- Tray
- Product Status:
- Active
- Type:
- Floating Point
- Interface:
- DMA, EMIF, HPI, McBSP, SPI
- Clock Rate:
- 140MHz
- Non-Volatile Memory:
- 128kB
- On-Chip RAM:
- 128kB
- Voltage - I/O:
- 3.30V
- Voltage - Core:
- 1.9V
- Operating Temperature:
- -55°C ~ 115°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 429-CFCBGA (27x27)
SM320C6701GLPW14 FAQ
1.How can I place an order for SM320C6701GLPW14 through Aetrix?
Please submit a Request for Quotation (RFQ) for SM320C6701GLPW14 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SM320C6701GLPW14 reliable?
The price and inventory of SM320C6701GLPW14 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SM320C6701GLPW14 is usually 5 days.
3.What payment methods are accepted for SM320C6701GLPW14?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SM320C6701GLPW14 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SM320C6701GLPW14?
SM320C6701GLPW14 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SM320C6701GLPW14 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SM320C6701GLPW14?
For technical support, including SM320C6701GLPW14 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SM320C6701GLPW14 requirements.
6.How does Aetrix verify that SM320C6701GLPW14 is sourced from the original manufacturer or authorized distributors?
All SM320C6701GLPW14 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SM320C6701GLPW14 meets industry standards.
7.What is the process for return or replacement of SM320C6701GLPW14?
All SM320C6701GLPW14 units undergo pre-shipment inspection (PSI). If there is an issue with SM320C6701GLPW14, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SM320C6701GLPW14 part is unused and in its original packaging.
Return procedure for SM320C6701GLPW14:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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