Texas Instruments SN65DSI84TPAPRQ1

Overview

SN65DSI84TPAPRQ1 from Texas Instruments is an automotive-grade MIPI DSI-to-dual-link LVDS bridge IC that converts single-channel DSI video streams (up to 4 Gbps input bandwidth) into dual-link LVDS outputs for TFT LCD displays. It supports 18-bpp RGB666 and 24-bpp RGB888 formats, operates at pixel clocks from 25 MHz to 154 MHz, and delivers WUXGA 1920 × 1200 @ 60 fps with full AEC-Q100 Grade 2 qualification (–40°C to 105°C).

For engineers reviewing the SN65DSI84TPAPRQ1 datasheet, SN65DSI84TPAPRQ1 pinout, SN65DSI84TPAPRQ1 application, or SN65DSI84TPAPRQ1 equivalent, key selection considerations include DSI lane configuration (1–4 lanes), LVDS output mode (single/dual-link), ULPS support, LVDS clock sourcing (DSI CLK or REFCLK), and HTQFP-64 thermal performance under automotive ambient conditions.

Technical Context

The SN65DSI84TPAPRQ1 implements a MIPI D-PHY v1.00.00 front-end with four configurable DSI data lanes (DA0P/N through DA3P/N) and one DSI clock lane (DACP/N), all supporting up to 1 Gbps per lane. Its internal PLL accepts either the DSI channel A HS clock (in free-running mode) or an external 25–154 MHz REFCLK to generate the LVDS pixel clock.

It features partial line buffering to reconcile DSI/LVDS timing mismatch, supports LVDS channel swap and pin-order reversal for PCB routing flexibility, and provides I²C-configurable CSR registers for LVDS format, test pattern generation, and power management-including SHUTDOWN, ULPS entry/exit, and reduced LVDS swing modes.

Key Specifications

Pinout & Package

SN65DSI84TPAPRQ1 is housed in a 64-pin HTQFP (PAP) package with exposed thermal pad (PowerPAD™), optimized for automotive thermal reliability and PCB layout density. Pin pitch is 0.5 mm; body size is 10.00 mm × 10.00 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DSI-to-LVDS bridge applications.

Compared with SN65DSI83TPAPRQ1 and DS90UH925QSQX/NOPB, SN65DSI84TPAPRQ1 uniquely delivers native dual-link LVDS conversion with full MIPI DSI protocol compliance, ULPS retention, and automotive-grade thermal/ESD performance in a single 64-pin HTQFP package-making it optimal for high-resolution automotive displays where DSI integration and timing determinism are critical.

Availability

SN65DSI84TPAPRQ1 is available at Aetrix Electronics and suitable for automotive infotainment head units, hybrid instrument clusters, rear-seat entertainment systems, and industrial HMI displays requiring stable component supply across extended temperature and lifecycle requirements.

Supply support for SN65DSI84TPAPRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive electronics with decades of automotive qualification expertise.

The SN65DSI84TPAPRQ1 belongs to TI's automotive display interface product line, designed specifically to bridge next-generation DSI-based application processors to legacy LVDS display modules in safety-compliant, thermally demanding vehicle environments.

FAQ

What is the maximum DSI data rate supported by the SN65DSI84TPAPRQ1?

The SN65DSI84TPAPRQ1 supports up to 1 Gbps per DSI data lane, with four configurable lanes (DA0P/N through DA3P/N) and one DSI clock lane (DACP/N), delivering a maximum input bandwidth of 4 Gbps. This enables full 24-bpp RGB888 video transport at resolutions including WUXGA 1920 × 1200 @ 60 fps. The device implements MIPI D-PHY v1.00.00 physical layer compliance for reliable high-speed signaling.

Does the SN65DSI84TPAPRQ1 support dual-link LVDS output?

Yes, the SN65DSI84TPAPRQ1 natively supports dual-link LVDS output with separate Channel A and Channel B LVDS interfaces. In dual-link mode, Channel A carries odd-pixel data and Channel B carries even-pixel data, enabling high-resolution timing for panels requiring >1366×768. The device also supports single-link LVDS operation and allows LVDS pin-order reversal and channel swap for simplified PCB routing.

How is the LVDS pixel clock generated in the SN65DSI84TPAPRQ1?

The SN65DSI84TPAPRQ1 generates the LVDS pixel clock from either the DSI channel A HS clock (in free-running continuous mode) or an external 25–154 MHz REFCLK input. Selection is controlled via CSR register HS_CLK_SRC (0x0A.0). When using REFCLK, the internal PLL multiplies it using REFCLK_MULTIPLIER (0x0B.1:0); when using DSI CLK, it divides using DSI_CLK_DIVIDER (0x0B.7:3). Both paths require proper LVDSPLL configuration and enablement.

What power supplies does the SN65DSI84TPAPRQ1 require?

The SN65DSI84TPAPRQ1 requires a 1.8 V VCC supply for I/O and logic, and derives a regulated 1.1 V VCORE internally for core circuitry-requiring a 1-µF external capacitor on the VCORE pin. All VCC pins must be decoupled with 0.1-µF ceramic capacitors close to the package. Total active current is 106–164 mA; standby current in ULPS is 7.7–14 mA, and shutdown current (EN = 0) is 0.04–130 µA.

Is the SN65DSI84TPAPRQ1 qualified for automotive applications?

Yes, the SN65DSI84TPAPRQ1 is AEC-Q100 qualified for automotive applications with Device Temperature Grade 2 (–40°C to +105°C ambient), HBM ESD Level 3A (±4 kV), and CDM ESD Level C6 (±1 kV). It is explicitly designed for infotainment head units, rear-seat displays, hybrid clusters, and industrial HMIs where automotive reliability, thermal resilience, and functional safety readiness are mandatory.