Texas Instruments SN65DSI84ZQER

Overview

SN65DSI84ZQER from Texas Instruments is a single-channel MIPI® DSI-to-FlatLink™ LVDS bridge IC that converts 1–4-lane D-PHY input (up to 1 Gbps/lane) into dual-link LVDS output with configurable 18/24-bit RGB video support, enabling WUXGA 1920×1200 @60 fps display interfaces in compact portable systems.

For engineers reviewing the SN65DSI84ZQER datasheet, SN65DSI84ZQER pinout, SN65DSI84ZQER application, or SN65DSI84ZQER equivalent, key selection criteria include DSI lane count flexibility, dual-link LVDS clock sourcing (DSI CLK or REFCLK), ULPS support, LVDS VOD programmability, and nFBGA-64 thermal performance at –40°C to 85°C.

Technical Context

The SN65DSI84ZQER implements a full MIPI D-PHY v1.00.00 receiver front-end with HS and LP mode handling, packet decoding for DSI 18bpp RGB666 and 24bpp RGB888, and partial line buffering to reconcile DSI/LVDS timing skew. Its internal PLL supports pixel clock generation from either continuous D-PHY clock or external REFCLK (25–154 MHz).

It features dual independent LVDS serializer channels (A and B), each with four data lanes + clock, programmable differential output voltage (180–488 mV), common-mode voltage control (0.8–1.35 V), and LVDS pin-order reversal for routing optimization - all managed via I²C-configurable CSR registers.

Key Specifications

Pinout & Package

Packaged in a 64-pin, 5.0 mm × 5.0 mm nFBGA (ZXH) with 0.5 mm pitch, optimized for high-density PCB layouts in portable displays.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DSI-to-LVDS bridge applications.

Compared with SN65DSI83ZQER, SN65DSI84ZQER delivers dual-link LVDS bandwidth for WUXGA+ panels; versus TC358743XBG, it offers smaller nFBGA footprint, native 1.8 V compatibility, and lower power - making it optimal for space- and power-constrained portable displays.

Availability

SN65DSI84ZQER is available at Aetrix Electronics and suitable for tablet display interfaces, notebook embedded displays, and industrial panel PCs requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SN65DSI84ZQER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog and embedded processing solutions with focus on reliability, precision, and energy efficiency.

The SN65DSI84ZQER belongs to TI's FlatLink™ bridge product line, designed specifically to enable seamless migration from MIPI DSI-based SoCs to legacy LVDS display ecosystems in portable and industrial computing.

FAQ

What is the maximum DSI data rate supported by the SN65DSI84ZQER?

The SN65DSI84ZQER supports up to 1 Gbps per D-PHY data lane, with configurable 1–4 lanes per channel. At four lanes, this yields a maximum DSI input bandwidth of 4 Gbps - sufficient for WUXGA 1920×1200 @60 fps with 24 bpp RGB888 video packets. The DSI clock lane operates up to 500 MHz in HS mode.

Does the SN65DSI84ZQER support both single-link and dual-link LVDS output configurations?

Yes, the SN65DSI84ZQER supports both single-link and dual-link LVDS output modes via I²C register configuration. In dual-link mode, it drives eight LVDS data lanes (four per link) plus two clock lanes (A_CLKP/N and B_CLKP/N), enabling high-resolution panels such as 1920×1200. Single-link mode uses only Channel A outputs.

How is the LVDS pixel clock generated in the SN65DSI84ZQER?

The SN65DSI84ZQER generates the LVDS pixel clock from either the DSI channel A HS clock (in free-running mode) or an external REFCLK input (25–154 MHz). Selection is controlled by CSR 0x0A.0 (HS_CLK_SRC), and the internal PLL is configured via CSR 0x0B and 0x0D to multiply/divide the source clock to match target pixel rates.

What power supplies are required for proper operation of the SN65DSI84ZQER?

The SN65DSI84ZQER requires a single 1.8 V VCC supply for I/O and logic, and derives its 1.1 V VCORE internally - which must be decoupled with a 1 µF ceramic capacitor to GND. Decoupling for VCC requires at minimum one 0.1 µF and one 0.01 µF capacitor placed near the device pins to suppress noise and ensure stable DSI/LVDS signaling.

Is ULPS (Ultra-Low Power State) supported on the SN65DSI84ZQER, and how is it implemented?

Yes, the SN65DSI84ZQER fully supports MIPI-defined ULPS. Entry requires host-driven LP11 sequences on all active DSI lanes; exit requires LP11 → LP01 → HS transition followed by ≥3 ms wait and soft reset (CSR 0x09.0). ULPS preserves I²C accessibility and reduces current to 7.7 mA typical, enabling rapid display wake-up without full reinitialization.