Texas Instruments SN65DSI84ZXHR

Overview

SN65DSI84ZXHR from Texas Instruments is a single-channel MIPI® DSI-to-FlatLink™ LVDS bridge IC that converts 1–4-lane D-PHY video streams (up to 1 Gbps/lane) into dual-link LVDS output for high-resolution displays. It supports RGB666 (18 bpp) and RGB888 (24 bpp), delivers up to 4 Gbps input bandwidth, operates at 1.8-V VCC, and targets WUXGA 1920 × 1200 @ 60 fps.

For engineers reviewing the SN65DSI84ZXHR datasheet, SN65DSI84ZXHR pinout, SN65DSI84ZXHR application, or SN65DSI84ZXHR equivalent, key selection considerations include DSI lane configuration flexibility, dual-link LVDS clock sourcing (DSI CLK or REFCLK), ULPS support, LVDS channel swap capability, and nFBGA-64 thermal performance in embedded display interfaces.

Technical Context

The SN65DSI84ZXHR implements a MIPI D-PHY v1.00.00 receiver front-end with configurable 1–4 data lanes per channel and a DSI v1.02.00 packet processor supporting short/long packets, SOT/EOT, and error detection. It features partial line buffering to reconcile DSI–LVDS timing skew and uses an internal PLL with programmable dividers/multipliers for pixel clock synthesis.

Its FlatLink™ LVDS output supports both single-link and dual-link modes with four data lanes per link, configurable differential voltage swing (180–488 mV), and common-mode voltage options (0.8–1.35 V). Clock source selection (DSI free-running HS clock or external REFCLK 25–154 MHz) and register-based control via I²C enable precise system-level timing alignment and power-state coordination.

Key Specifications

Pinout & Package

Packaged in a 64-pin 5-mm × 5-mm nFBGA (ZXH) with 0.5-mm pitch, the SN65DSI84ZXHR integrates dedicated DSI input lanes (DA0P/N through DA3P/N, DACP/N), dual-channel LVDS outputs (A_Y0P/N–A_Y3P/N, B_Y0P/N–B_Y3P/N, A/B_CLKP/N), I²C interface (SCL/SDA), interrupt (IRQ), chip enable (EN), and reference clock (REFCLK).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DSI-to-LVDS bridge applications.

Compared with SN65DSI83ZXHR, the SN65DSI84ZXHR adds dual-link LVDS capability essential for WUXGA+ panels; compared with TC358743XBG, it offers lower power, smaller footprint, and simpler register interface-but no HDMI or security features.

Availability

SN65DSI84ZXHR is available at Aetrix Electronics and suitable for notebook display subsystems, industrial panel PCs, embedded tablet interfaces, and connected peripheral display modules requiring stable component supply and long-term design-in support.

Supply support for SN65DSI84ZXHR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies with broad industrial and automotive qualification.

The SN65DSI84ZXHR belongs to TI's FlatLink™ display interface product line, designed specifically to bridge mobile-oriented DSI interfaces to legacy LVDS display panels in space-constrained, power-sensitive applications.

FAQ

What is the maximum DSI data rate supported by the SN65DSI84ZXHR?

The SN65DSI84ZXHR supports up to 1 Gbps per D-PHY data lane, with configurable 1–4 lanes per channel. At full 4-lane operation, this yields a maximum input bandwidth of 4 Gbps-sufficient for 24-bpp WUXGA 1920 × 1200 video at 60 fps. The DSI clock lane (DACP/N) operates up to 500 MHz in HS mode, and the device requires continuous free-running DSI clock for internal PLL locking when REFCLK is not used.

Does the SN65DSI84ZXHR support both RGB666 and RGB888 color formats?

Yes, the SN65DSI84ZXHR decodes MIPI DSI video packets in both 18-bpp RGB666 and 24-bpp RGB888 formats. It automatically detects packet type and configures LVDS serialization accordingly. For 18-bpp operation, A_Y3P/A_Y3N and B_Y3P/B_Y3N pins must be left unconnected per datasheet guidance, reducing routing complexity on the PCB.

How does the SN65DSI84ZXHR handle power management during display idle periods?

The SN65DSI84ZXHR implements full MIPI-defined ultra-low power state (ULPS) support. When all active DSI lanes enter ULPS (LP00), device current drops to 7.7 mA typical. ULPS entry/exit is hardware-managed, and CSR registers remain accessible via I²C during ULPS-allowing host firmware to monitor status or reconfigure without exiting low-power mode.

Can the SN65DSI84ZXHR generate LVDS test patterns without a DSI source?

Yes, the SN65DSI84ZXHR includes an on-chip LVDS pattern generator enabled by setting CHA_TEST_PATTERN bit (CSR address 0x3C). When activated, it drives predefined test patterns (solid color, checkerboard, ramp) on both LVDS links-enabling validation of LVDS PHY integrity, cable/connector continuity, and panel functionality prior to DSI video initialization.

What is the recommended decoupling strategy for the SN65DSI84ZXHR power supplies?

Texas Instruments recommends placing four ceramic capacitors near the SN65DSI84ZXHR power pins: two 0.1 µF and two 0.01 µF devices. At minimum, one 0.1 µF and one 0.01 µF capacitor should be placed adjacent to each VCC pin, with trace lengths minimized to reduce inductance. Mounting decoupling capacitors underneath the nFBGA on the PCB bottom layer is preferred to maintain low-impedance paths and suppress high-frequency noise.