Texas Instruments SN65DSI85TPAPRQ1

Overview

SN65DSI85TPAPRQ1 from Texas Instruments is an AEC-Q100 Grade 2 automotive dual-channel MIPI DSI-to-LVDS bridge IC that converts 18-/24-bpp RGB666/RGB888 video streams over two D-PHY channels (up to 4 lanes/channel, 1 Gbps/lane) into dual-link LVDS output with pixel clock range 25–154 MHz. It supports WQXGA 2560×1600 @60 fps and WUXGA 1920×1200 @120 fps equivalent for infotainment displays.

For engineers reviewing the SN65DSI85TPAPRQ1 datasheet, SN65DSI85TPAPRQ1 pinout, SN65DSI85TPAPRQ1 application, or SN65DSI85TPAPRQ1 equivalent, key selection criteria include DSI lane configuration flexibility (1–4 lanes per channel), LVDS link mode (single/dual/two single-link), ULPS support, 1.8-V VCC supply, and HTQFP-64 thermal performance in –40°C to 105°C ambient.

Technical Context

The device implements a dual-channel MIPI D-PHY 1.00.00 front-end with configurable lane count per channel and decodes DSI video packets before formatting pixel data for LVDS serialization. Its internal PLL locks to either the DSI clock or external REFCLK (25–154 MHz) to generate precise LVDS pixel timing.

It features partial line buffering to absorb DSI–LVDS data rate mismatch, supports odd/even and left/right DSI channel mapping, and provides LVDS pin-order reversal and channel swap for PCB routing optimization. All LVDS outputs are fully differential with programmable swing (180–535 mV) and common-mode voltage (0.75–1.5 V).

Key Specifications

Pinout & Package

SN65DSI85TPAPRQ1 is packaged in a 64-pin HTQFP (PAP) with 10 mm × 10 mm body and 0.5-mm pitch, featuring exposed PowerPAD™ thermal pad for enhanced heat dissipation in automotive environments.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DSI-to-LVDS bridge applications.

Compared with SN65DSI84TPAPRQ1, SN65DSI85TPAPRQ1 delivers dual-channel scalability and dual-link LVDS for higher-resolution panels; versus DS90UH940NQSQEVM, it offers direct DSI integration without serializer-deserializer pairing, reducing component count and latency.

Availability

SN65DSI85TPAPRQ1 is available at Aetrix Electronics and suitable for automotive infotainment head units, hybrid instrument clusters, and industrial HMIs requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for SN65DSI85TPAPRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive electronics, with decades of experience in display interface solutions and AEC-Q100-qualified components.

The SN65DSI85TPAPRQ1 belongs to TI's automotive display bridge product line, engineered specifically for MIPI DSI-to-LVDS translation in safety-critical, thermally demanding vehicle display systems.

FAQ

What is the maximum DSI data rate supported by the SN65DSI85TPAPRQ1?

The SN65DSI85TPAPRQ1 supports up to 1 Gbps per D-PHY data lane, with dual-channel configuration allowing up to 4 lanes per channel. This yields a maximum aggregate DSI input bandwidth of 8 Gbps, sufficient for 24-bpp WQXGA video at 60 fps. The device complies with MIPI D-PHY v1.00.00 and DSI v1.02.00 specifications, ensuring interoperability with standard DSI sources.

Does the SN65DSI85TPAPRQ1 require external configuration via I²C?

Yes, the SN65DSI85TPAPRQ1 requires I²C-based register initialization after power-up and reset. Critical registers-including PLL_EN (CSR 0x0D.0), SOFT_RESET (CSR 0x09.0), and LVDS format controls (e.g., CSR 0x18)-must be written in sequence before video transmission begins. The SCL/SDA pins and ADDR pin enable local configuration without host processor firmware changes.

Can the SN65DSI85TPAPRQ1 drive an 18-bpp LVDS panel?

Yes, the SN65DSI85TPAPRQ1 natively supports 18-bpp RGB666 output. When configured for 18-bpp mode, the A_Y3P/N and B_Y3P/N LVDS lanes are disabled (NC), and pixel data is mapped across the remaining three data lanes per channel. This avoids overscan or truncation issues and maintains timing alignment with legacy 18-bpp panels.

How does the SN65DSI85TPAPRQ1 handle ultra-low power state (ULPS) transitions?

The SN65DSI85TPAPRQ1 fully implements MIPI D-PHY ULPS entry and exit protocols. During ULPS, all DSI lanes enter low-power mode with controlled voltage thresholds (VIL-ULPS ≤300 mV), and the device draws only 7.7–14 mA. Exit timing adheres to D-PHY spec requirements, ensuring glitch-free resumption of high-speed video streaming without host intervention.

What thermal management provisions does the SN65DSI85TPAPRQ1 include?

The SN65DSI85TPAPRQ1 uses a 64-pin HTQFP package with integrated PowerPAD™ thermal pad, achieving R_θJA = 36.1°C/W and R_θJB = 20.6°C/W. For automotive applications, this allows direct thermal coupling to copper pour or heatsink, sustaining 105°C ambient operation without derating. Layout guidelines recommend minimum 4-layer board with dedicated ground/power planes and thermal vias under the PowerPAD™.