Texas Instruments SN65DSI85ZQER

Overview

SN65DSI85ZQER from Texas Instruments is a dual-channel MIPI DSI-to-FlatLink LVDS bridge IC that converts 18-bpp/24-bpp RGB666/RGB888 video streams over two D-PHY channels (up to 4 lanes per channel at 1 Gbps/lane) into dual-link or single-link LVDS output. It supports WQXGA 2560×1600 @ 60 fps and WUXGA 1920×1200 with 3D graphics @ 120 fps equivalent, operating from –40°C to 85°C in a 5 mm × 5 mm nFBGA-64 package.

For engineers reviewing the SN65DSI85ZQER datasheet, SN65DSI85ZQER pinout, SN65DSI85ZQER application, or SN65DSI85ZQER equivalent, this page delivers verified technical context, exact pin functions, real-world timing and power specifications, validated alternative parts, and design-critical interface behavior - all grounded in TI's official SLLSEB9G revision G documentation.

Technical Context

The SN65DSI85ZQER implements a dual-channel MIPI D-PHY 1.00.00 front-end with configurable lane count (1–4 per channel), supporting both ODD/EVEN and LEFT/RIGHT DSI channel mapping modes. Its internal PLL generates FlatLink LVDS pixel clocks from either the DSI Channel A HS clock (free-running mode) or an external REFCLK (25–154 MHz).

It features partial line buffering to reconcile DSI/LVDS data rate mismatches, programmable LVDS output swing (180–488 mV differential), and full MIPI ULPS entry/exit support with CSR-register accessibility during low-power states. The device decodes DSI short/long packets and outputs synchronized LVDS data across two independent links (A and B), each with four data lanes + clock pair.

Key Specifications

Pinout & Package

SN65DSI85ZQER is packaged in a 64-pin nFBGA (ZXH) with 0.5 mm pitch and 5.0 mm × 5.0 mm body size. Pin assignments follow TI's standardized top-view layout with dedicated DSI lane pairs (DA0–DA3, DB0–DB3), LVDS channel A/B data/clock outputs (A_Y0P/N through A_CLKP/N, B_Y0P/N through B_CLKP/N), I²C interface (SCL/SDA), interrupt (IRQ), enable/reset (EN), and reference clock (REFCLK).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DSI-to-LVDS bridge applications.

Compared with SN65DSI84ZQER and DS90UH925QSQ/NOPB, SN65DSI85ZQER uniquely delivers dual-channel DSI reception with dual-link LVDS output in a single chip - enabling native WQXGA support, flexible lane mapping, and direct integration with dual-DPU SoCs without protocol translation overhead.

Availability

SN65DSI85ZQER is available at Aetrix Electronics and suitable for high-resolution notebook displays, tablet main interfaces, industrial panel PCs, and medical imaging displays requiring stable component supply, long-term lifecycle assurance, and automotive-grade reliability validation.

Supply support for SN65DSI85ZQER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of display interface IP development and automotive-qualified manufacturing.

The SN65DSI85ZQER belongs to TI's FlatLink bridge product line, designed specifically to simplify high-bandwidth mobile display interfacing between MIPI DSI-enabled application processors and legacy LVDS panels in space-constrained consumer and industrial systems.

FAQ

What is the maximum DSI lane speed supported by the SN65DSI85ZQER?

The SN65DSI85ZQER supports up to 1 Gbps per DSI data lane, with dual-channel operation allowing up to 4 lanes per channel. This yields a maximum aggregate input bandwidth of 8 Gbps, sufficient for WQXGA 2560×1600 @ 60 fps with 24-bpp RGB888. The DSI clock lane operates up to 500 MHz in HS mode, and the device requires free-running DSI CLK for internal LVDS clock generation unless REFCLK is used.

Does the SN65DSI85ZQER support both RGB666 and RGB888 color formats?

Yes, the SN65DSI85ZQER natively decodes MIPI DSI video packets in both 18-bpp RGB666 and 24-bpp RGB888 formats. Format selection is automatic based on incoming DSI stream configuration and does not require register programming. The device routes pixel data accordingly to its LVDS outputs, maintaining bit-perfect fidelity for both formats across all supported resolutions and frame rates.

How is the LVDS pixel clock generated in the SN65DSI85ZQER?

The SN65DSI85ZQER generates the LVDS pixel clock from either the DSI Channel A HS clock (free-running mode) or an external REFCLK input (25–154 MHz). Selection is controlled via CSR register bit HS_CLK_SRC (0x0A.0). When using DSI CLK, the internal PLL divides the input frequency using DSI_CLK_DIVIDER (0x0B.7:3); when using REFCLK, it multiplies the input using REFCLK_MULTIPLIER (0x0B.1:0). Both paths require proper LVDS_CLK_RANGE (0x0A.3:1) setup.

Can the SN65DSI85ZQER operate in ultra-low power state (ULPS) while retaining configuration access?

Yes, the SN65DSI85ZQER fully supports MIPI-defined ULPS with CSR register accessibility maintained via I²C during ULPS. The device accepts ULPS entry/exit sequences on active DSI lanes, and all configuration registers remain readable and writable - enabling dynamic power-state transitions without host firmware reset or reinitialization. ULPS current draw is 7.7 mA typical, significantly lower than active mode (127–212 mA).

What package type and pin count does the SN65DSI85ZQER use?

The SN65DSI85ZQER uses a 64-pin nFBGA package (TI designation ZXH), with nominal dimensions of 5.0 mm × 5.0 mm and 0.5 mm ball pitch. This compact, thermally efficient package supports high-density PCB layouts and is qualified for reflow soldering per JEDEC J-STD-020. Pin functions are documented in Table 5-1 of the SLLSEB9G datasheet, including dedicated DSI input lanes, LVDS output pairs, I²C interface, and REFCLK input.