Texas Instruments SN65DSI85ZXHR

Overview

SN65DSI85ZXHR from Texas Instruments is a dual-channel MIPI DSI-to-FlatLink LVDS bridge IC that converts 18-bpp/24-bpp DSI video streams (RGB666/RGB888) into dual-link or single-link LVDS outputs, supporting up to 2560 × 1600 @60 fps and WUXGA 1920 × 1200 @120 fps equivalent in 3D graphics applications. It features dual 4-lane D-PHY receivers (1 Gbps/lane), configurable LVDS output clock range (25–154 MHz), and 1.8-V main supply.

For engineers reviewing the SN65DSI85ZXHR datasheet, SN65DSI85ZXHR pinout, SN65DSI85ZXHR application, or SN65DSI85ZXHR equivalent, key selection considerations include DSI lane configuration flexibility (1–4 lanes/channel), LVDS link mode selection (single/dual/two-single), ULPS support for power gating, LVDS voltage swing programmability, and BGA MICROSTAR JUNIOR (64-pin, 5 mm × 5 mm) package compatibility with high-density mobile display interfaces.

Technical Context

The SN65DSI85ZXHR implements a dual-channel MIPI D-PHY 1.00.00 physical layer front-end with independent lane merging logic per channel, enabling ODD/EVEN or LEFT/RIGHT DSI data routing. Its internal PLL generates LVDS pixel clocks either from the free-running DSI channel A clock (40–500 MHz) or an external REFCLK (25–154 MHz), with programmable dividers/multipliers via I²C-configurable CSR registers.

It supports partial line buffering to absorb DSI–LVDS timing skew, decodes DSI short/long packets including video stream headers and EOT markers, and delivers FlatLink-compatible LVDS outputs with configurable differential voltage swing (180–488 mV) and common-mode voltage (0.8–1.35 V) across eight data lanes and two clock lanes - all while maintaining MIPI-compliant ULPS entry/exit sequences and failsafe LP/HS receiver thresholds.

Key Specifications

Pinout & Package

Packaged in a 64-pin BGA MICROSTAR JUNIOR (ZQE) with 0.5-mm pitch and 5.00 mm × 5.00 mm body size, optimized for compact mobile display interface layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DSI-to-LVDS bridge applications.

Compared with SN65DSI84ZXHR and SN75DP130RGZR, the SN65DSI85ZXHR uniquely supports dual-channel DSI reception, dual-link LVDS output, and MIPI ULPS - making it the only viable option for high-resolution mobile displays requiring full DSI protocol compliance and power-aware operation.

Availability

SN65DSI85ZXHR is available at Aetrix Electronics and suitable for tablet PC, notebook PC, and mobile internet device applications requiring stable component supply, long-lifecycle support, and automotive-grade reliability validation.

Supply support for SN65DSI85ZXHR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of experience in display interface solutions and automotive-qualified product development.

The SN65DSI85ZXHR belongs to TI's FlatLink™ bridge product line, designed specifically to enable seamless migration from legacy LVDS display panels to modern MIPI DSI-based application processors in space-constrained mobile and industrial systems.

FAQ

What is the maximum DSI data rate supported by the SN65DSI85ZXHR?

The SN65DSI85ZXHR supports up to 1 Gbps per D-PHY data lane across both channels, delivering a total input bandwidth of 8 Gbps. This enables full support for WQXGA (2560 × 1600) at 60 fps with 24-bpp RGB888 format. The DSI clock lane operates up to 500 MHz in HS mode, and the device complies with MIPI D-PHY v1.00.00 and DSI v1.02.00 specifications. All lane speed ratings are verified under recommended operating conditions (VCC = 1.65–1.95 V, TA = –40°C to +85°C).

Can the SN65DSI85ZXHR generate LVDS pixel clocks from its internal DSI clock input?

Yes, the SN65DSI85ZXHR can derive the LVDS pixel clock directly from the DSI channel A clock lane (DACP/DACN) when configured in free-running HS mode. This eliminates the need for an external crystal oscillator or clock generator. The internal PLL divides the DSI clock using the DSI_CLK_DIVIDER register (CSR 0x0B.7:3), and the LVDS clock range must be set via LVDS_CLK_RANGE (CSR 0x0A.3:1) to ensure correct PLL lock. The SN65DSI85ZXHR supports DSI clock frequencies from 40 MHz to 500 MHz for this mode.

Does the SN65DSI85ZXHR support MIPI Ultra-Low Power State (ULPS)?

Yes, the SN65DSI85ZXHR fully implements MIPI-defined ULPS entry and exit sequences per D-PHY specification. During ULPS, the device draws only 7.7 mA typical current, maintains I²C accessibility for register monitoring, and retains configuration state. ULPS is initiated by driving all active DSI data and clock lanes to LP11, followed by a minimum 3-ms wait and soft reset (CSR 0x09.0). The SN65DSI85ZXHR supports ULPS on both DSI channels independently, enabling selective power gating.

What LVDS configurations does the SN65DSI85ZXHR support?

The SN65DSI85ZXHR supports three LVDS output modes: dual-link LVDS (eight data lanes + two clocks), single-link LVDS (four data lanes + one clock), or two independent single-link LVDS interfaces (four data lanes + one clock each). Configuration is controlled via CSR registers and does not require hardware changes. The device also provides LVDS pin order reverse and lane swap features to simplify PCB routing - particularly valuable in tight-layout mobile designs where trace length matching is critical.

Is the SN65DSI85ZXHR compatible with 18-bpp and 24-bpp display panels?

Yes, the SN65DSI85ZXHR natively supports both 18-bpp RGB666 and 24-bpp RGB888 DSI video packet formats. It decodes incoming DSI packets, reconstructs pixel data, and maps it to FlatLink™-compliant LVDS timing with appropriate blanking intervals. For 18-bpp panels, A_Y3P/A_Y3N and B_Y3P/B_Y3N pins are left unconnected per datasheet guidance. The SN65DSI85ZXHR has been validated for WQXGA 2560 × 1600 at 60 fps in both formats, ensuring accurate color reproduction and timing fidelity.