Texas Instruments SN65DSI86ZQER

Overview

SN65DSI86ZQER from Texas Instruments is a dual-channel MIPI D-PHY receiver to embedded DisplayPort (eDP) 1.4 bridge IC, supporting up to 4-lane eDP at 5.4 Gbps (HBR2), 24 bpp RGB888 video, and WUXGA 1920×1200 at 60 fps with 3D graphics capability. It operates from 1.2-V core and 1.8-V I/O supplies, features ULPS support, and targets high-resolution display interconnect in space-constrained portable systems.

For engineers reviewing the SN65DSI86ZQER datasheet, SN65DSI86ZQER pinout, SN65DSI86ZQER application, or SN65DSI86ZQER equivalent, key selection criteria include DSI-to-eDP protocol translation fidelity, HBR2 lane rate compatibility, dual-channel D-PHY configuration flexibility, thermal performance in 5-mm × 5-mm nFBGA, and I²C-based register programmability for timing and power modes.

Technical Context

The SN65DSI86ZQER implements a full MIPI DSI 1.02.00 decoder front-end with configurable dual-channel D-PHY (up to 4 lanes per channel, 1.5 Gbps/lane), followed by an eDP 1.4 transmitter with programmable main link rates (RBR/HBR/HBR2) and AUX channel support. It includes partial line buffering to reconcile DSI and eDP data stream timing mismatches.

Its architecture supports both odd/even and left/right DSI channel mapping, configurable DP lane polarity and assignment, and dual reference clock options (external REFCLK or D-PHY clock feed). Power management integrates panel refresh control and MIPI ULPS entry/exit coordination across both interfaces.

Key Specifications

Pinout & Package

SN65DSI86ZQER is packaged in a 64-ball, 5.0 mm × 5.0 mm nFBGA (ZXH) with 0.5-mm ball pitch. The package supports thermal dissipation via bottom-side solder joints and is compatible with standard reflow profiles for lead-free assembly.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DSI-to-eDP bridge applications.

Compared with SN65DSI84ZQER, SN65DSI86ZQER delivers 2× eDP bandwidth (5.4 vs. 2.7 Gbps) and dual DSI channels for independent display control; versus TC358772XBG, it offers lower power, smaller footprint, and simpler configuration - ideal for cost-sensitive, high-resolution portable designs without HDCP or audio demands.

Availability

SN65DSI86ZQER is available at Aetrix Electronics and suitable for tablet display interfaces, industrial panel PCs, retail kiosks, and medical diagnostic monitors requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SN65DSI86ZQER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, personal electronics, and communications markets.

The SN65DSI86ZQER belongs to TI's high-speed interface bridge product line, designed specifically to solve display connectivity challenges between mobile application processors and modern eDP-based LCD panels in portable and embedded systems.

FAQ

What display resolutions does the SN65DSI86ZQER support at 60 fps?

The SN65DSI86ZQER supports WUXGA (1920×1200) at 60 fps with 24 bpp RGB888 and 4K (4096×2304) at 60 fps with 18 bpp RGB666. Its 12 Gbps maximum DSI input bandwidth and HBR2 eDP output enable these resolutions without compression or frame dropping. The SN65DSI86ZQER achieves this through dual-channel D-PHY reception and partial line buffering that aligns burst-mode DSI traffic with continuous eDP streaming.

Does the SN65DSI86ZQER require an external reference clock?

No, the SN65DSI86ZQER supports two reference clock sources: an external 12/19.2/26/27/38.4 MHz oscillator on REFCLK, or the DACP/N D-PHY clock lane directly feeding the DisplayPort PLL. This eliminates the need for an external crystal in many designs. The SN65DSI86ZQER automatically selects the active source based on register configuration and EN assertion timing, simplifying bill-of-materials and layout.

How does the SN65DSI86ZQER handle power management during display idle periods?

The SN65DSI86ZQER implements coordinated MIPI ULPS and eDP panel self-refresh (PSR) entry/exit. When the DSI interface enters ULPS, the SN65DSI86ZQER can trigger eDP PSR mode to maintain display content while reducing system power by >90%. The SN65DSI86ZQER retains full register state and resumes normal operation within microseconds upon wake-up, ensuring seamless user experience.

Can the SN65DSI86ZQER be used in dual-display configurations?

Yes, the SN65DSI86ZQER supports dual-display operation via its dual-channel DSI receiver: Channel A and Channel B can drive separate eDP panels independently, or be combined for single-panel high-bandwidth operation. The SN65DSI86ZQER allows per-channel lane count configuration (1–4 lanes), odd/even or left/right mapping, and independent timing registers - enabling synchronized or asynchronous dual-display topologies.

What is the thermal performance of the SN65DSI86ZQER in its nFBGA package?

The SN65DSI86ZQER in the 64-ball nFBGA (ZXH) package has a junction-to-ambient thermal resistance (RθJA) of 55.0°C/W and junction-to-board (RθJB) of 31.0°C/W under high-K board conditions. Its thermal design supports continuous operation at full HBR2 load (5.4 Gbps × 4 lanes) within the –40°C to +85°C ambient range when using standard 2-layer or 4-layer PCBs with adequate copper pour and thermal vias beneath the package.