Texas Instruments SN65DSI86ZXHR

Overview

SN65DSI86ZXHR from Texas Instruments is a MIPI DSI-to-eDP bridge IC supporting dual-channel DSI input (up to 4 lanes per channel at 1.5 Gbps) and eDP 1.4 output (1–4 lanes at 1.62–5.4 Gbps), delivering 12 Gbps max input bandwidth for RGB666/RGB888 video. It enables 4K@60fps (18 bpp) and WUXGA@60fps with 3D graphics in notebook and tablet display subsystems.

For engineers reviewing the SN65DSI86ZXHR datasheet, SN65DSI86ZXHR pinout, SN65DSI86ZXHR application, or SN65DSI86ZXHR equivalent, key selection criteria include DSI lane configuration flexibility, eDP HBR2 compliance, I²C programmability, ULPS support, and nFBGA-64 thermal performance in space-constrained embedded displays.

Technical Context

The SN65DSI86ZXHR implements a dual-channel MIPI D-PHY 1.1 front-end with configurable odd/even or left/right DSI routing and partial line buffering to reconcile DSI–eDP data rate mismatch. Its DisplayPort transmitter supports all eDP 1.4 link rates (RBR/HBR/HBR2) with programmable differential voltage levels (300–920 mVpp) and pre-emphasis (0–7.2 dB).

It features independent power domains: 1.2-V VCC/VCCA for core/analog circuits, 1.8-V VCCIO for digital I/O, and 1.8-V VPLL for the DisplayPort PLL. Configuration is performed via I²C interface with ADDR-selectable slave address, and operation supports REFCLK (12–38.4 MHz) or DACP/N as PLL reference.

Key Specifications

Pinout & Package

SN65DSI86ZXHR is packaged in a 64-ball, 5.0 mm × 5.0 mm nFBGA (package code ZXH) with 0.5-mm ball pitch and bottom-side thermal pad. The package supports standard reflow profiles and provides low thermal resistance (R_θJA = 55.0°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DSI-to-eDP bridge applications.

Compared with SN65DSI84ZXHR and CH7511B-DS, the SN65DSI86ZXHR uniquely delivers dual-channel DSI with full HBR2 eDP support, enabling true 4K@60fps in thermally constrained designs-making it the only option among the three qualified for next-generation high-resolution embedded displays requiring both bandwidth and configurability.

Availability

SN65DSI86ZXHR is available at Aetrix Electronics and suitable for notebook displays, retail kiosks, industrial HMIs, and test equipment requiring stable component supply, long-term manufacturability, and automotive-grade reliability validation.

Supply support for SN65DSI86ZXHR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies with leadership in interface, power management, and signal chain solutions.

The SN65DSI86ZXHR belongs to TI's Display Interface product line, engineered specifically for high-bandwidth, low-power mobile display interconnects between application processors and eDP panels in space- and power-constrained systems.

FAQ

What display resolutions does the SN65DSI86ZXHR support at 60 fps?

The SN65DSI86ZXHR supports 4K (4096×2304) at 60 fps with 18 bpp RGB666 and WUXGA (1920×1200) with 3D graphics at 60 fps (120 fps equivalent). Its 12 Gbps input bandwidth and HBR2 eDP output enable these resolutions without compression or frame buffering delay. The SN65DSI86ZXHR achieves this using dual-channel DSI with partial line buffering to align data streams across interfaces.

Does the SN65DSI86ZXHR require an external crystal or oscillator?

No, the SN65DSI86ZXHR does not require an external crystal. It accepts a single-ended REFCLK input at 12/19.2/26/27/38.4 MHz, or alternatively uses the DSI clock (DACP/N) as the DisplayPort PLL reference-eliminating the need for a dedicated oscillator. This flexibility reduces BOM cost and PCB area. The SN65DSI86ZXHR's internal PLL locks to either source with stable jitter performance per eDP 1.4 spec.

How is the SN65DSI86ZXHR configured during system startup?

The SN65DSI86ZXHR is configured via its I²C interface (SCL/SDA pins) using a target address set by the ADDR pin (0x38–0x3F). Configuration includes DSI lane count, eDP link rate, VOD level, pre-emphasis, and power modes. Default settings apply on power-up, but full register control is available before EN deassertion. The SN65DSI86ZXHR supports both hardware (GPIO latching) and software (I²C) configuration methods for production flexibility.

What power supply sequencing is required for reliable operation of the SN65DSI86ZXHR?

The SN65DSI86ZXHR requires VCC/VCCA to stabilize before VCCIO/VPLL (≥100 µs), and REFCLK must be active before EN assertion. All supplies must ramp within 0.2–100 ms. Violating sequencing risks incomplete initialization or register corruption. The SN65DSI86ZXHR integrates power-on reset circuitry but relies on controlled ramp rates to ensure analog blocks settle correctly-especially critical for DSI receiver sensitivity and eDP transmitter eye quality.

Can the SN65DSI86ZXHR operate in ultra-low power states during display idle periods?

Yes, the SN65DSI86ZXHR supports MIPI-defined ULPS on DSI lanes and panel refresh mode for eDP links. When SUSPEND is asserted, it powers down main link transmitters while retaining AUX channel readiness and HPD monitoring. Current drops to ≤11 mA total (ISUSPEND_CCA + ISUSPEND_CC + ISUSPEND_CCIO). The SN65DSI86ZXHR resumes full operation within microseconds of SUSPEND deassertion, maintaining seamless user experience during brief display inactivity.