Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Signal Switches, Multiplexers, Decoders

Texas Instruments SN65LVDS125ADBT

Name: SN65LVDS125ADBT
Brand: Texas Instruments
SKU: SN65LVDS125ADBT
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SN65LVDS125ADBT

Manufacturer:: Texas Instruments

Category:: Signal Switches, Multiplexers, Decoders

Package:: 38-TFSOP (0.173", 4.40mm Width)

Datasheet:: SN65LVDS125ADBT.pdf

Description:: IC CROSSPOINT SW 1 X 4:4 38TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,475

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SN65LVDS125ADBT from Texas Instruments is a 4×4 non-blocking LVDS crosspoint switch IC designed for high-speed signal routing in telecom, datacom, and HDTV video systems. It supports signaling rates up to 1.5 Gbps per channel, operates from a single 3.3-V supply, and features 900-ps typical propagation delay with ≤150-ps channel-to-channel output skew. It routes differential LVDS inputs (1A/1B–4A/4B) to any of four differential outputs (1Y/1Z–4Y/4Z) under S10–S41 control.

For engineers reviewing the SN65LVDS125ADBT datasheet, SN65LVDS125ADBT pinout, SN65LVDS125ADBT application, or SN65LVDS125ADBT equivalent, this device is selected for deterministic low-skew switching in OC-12 clock distribution, SMPTE 292 video transport, and multi-channel high-speed network routing where sub-nanosecond timing integrity and LVDS compliance are critical.

Technical Context

The SN65LVDS125ADBT implements a fully differential 4×4 crosspoint architecture with independent 4:1 multiplexers per output channel, enabling any input to be routed to any output without blocking. Its internal signal paths maintain strict differential balance to minimize skew and preserve eye integrity at 1.5 Gbps.

It accepts LVDS, LVPECL, and CML input levels and delivers ANSI TIA/EIA-644-A-compliant LVDS outputs with 247–454 mV differential voltage magnitude and 1.125–1.375 V steady-state common-mode voltage. Input hysteresis is 25 mV, and disable control (1DE–4DE) enables high-impedance output states with 300-ns enable/disable timing.

Key Specifications

Parameter	Value and Actual Design Meaning
Signaling Rate	Up to 1.5 Gbps per channel - supports SMPTE 292 (1.485 Gbps) and OC-12 (622 MHz) clock distribution.
Propagation Delay	700–1200 ps - ensures tight timing alignment across all 4 channels for synchronous multi-lane systems.
Channel Skew	≤150 ps max - guarantees sub-bit-period alignment between outputs in parallel data paths.
Differential Output Voltage	247–454 mV - meets LVDS standard drive strength while maintaining noise margin over process/voltage/temperature.
Supply Voltage	3.0–3.6 V - single-rail operation compatible with 3.3-V system power domains and LDO regulation.
Operating Temperature	−40°C to +85°C - qualified for industrial and telecom infrastructure environments.
Input Compatibility	LVDS/LVPECL/CML - eliminates level-shifting components when interfacing with diverse serializer/deserializer sources.

Pinout & Package

TSSOP-38 (DBT) package, 9.75 mm × 4.45 mm × 1.2 mm max height, RoHS-compliant, moisture sensitivity level 2 (260°C peak reflow).

Pin/Terminal	Circuit Role	Design Meaning
1A–4A, 1B–4B	LVDS differential input pairs	Accepts true differential signals; each pair maps to one of four input channels (A = positive, B = negative leg).
1Y–4Y, 1Z–4Z	LVDS differential output pairs	Delivers ANSI-compliant LVDS outputs; Y = positive, Z = negative leg; fully buffered and terminated internally.
S10–S41	Output channel select control inputs	Two-bit binary control per output (e.g., S10/S11 selects source for 1Y/1Z); enables non-blocking 4:1 mux per output.
1DE–4DE	Output disable inputs	Active-low enables high-Z state on corresponding Y/Z pair; supports dynamic output gating without signal contention.
VCC, GND	Power and ground terminals	Single 3.3-V supply; multiple VCC/GND pins distributed across package to reduce PSRR and improve high-frequency decoupling.

Key Features

Feature	Design Value
Non-blocking 4×4 crosspoint	Each output independently routes to any input - enables flexible signal fanout/fanin without path contention in multi-source systems.
LVDS compliance	Fully conforms to ANSI TIA/EIA-644-A - ensures interoperability with industry-standard LVDS transceivers and backplanes.
Low channel skew	≤150 ps max output-to-output skew - preserves timing margins in parallel clock/data buses like JESD204B or video pixel lanes.
Integrated input hysteresis	25 mV differential hysteresis - improves noise immunity on control and data lines in electrically noisy telecom chassis.
High-speed enable/disable	300-ns max transition to/from high-Z - allows dynamic output muting during hot-swap or fault recovery without glitch propagation.

Applications

Wireless Base Station Clock Distribution	HDTV Video Routing
Use Scenario: Distributing synchronized OC-12 or 1.485-Gbps SMPTE 292 clocks across multiple RF transceiver modules in LTE/5G macro base stations. IC Role / Device Role / Timing Role: Low-skew 4×4 LVDS crosspoint switch that routes master reference clocks to multiple downstream PLLs and ADC/DAC clock inputs. Use Value: Maintains <150-ps channel skew across all four outputs, preserving setup/hold timing for multi-chip synchronization and reducing bit error rate in high-order QAM modulation.	Use Scenario: Switching uncompressed HD-SDI video streams between multiple camera inputs and display/encoder outputs in broadcast production switchers. IC Role / Device Role / Timing Role: High-fidelity LVDS signal router handling 1.485-Gbps serial digital video with minimal jitter accumulation and no signal degradation. Use Value: Delivers 65–110 ps peak-to-peak jitter at 1.5 Gbps, preserving eye opening for reliable 10-bit video sampling and avoiding frame sync loss.
High-Speed Network Router Fabric	Test Equipment Signal Multiplexing
Use Scenario: Interconnecting multiple line-card SerDes outputs to centralized packet processing ASICs in 10G/25G Ethernet routers. IC Role / Device Role / Timing Role: Reconfigurable LVDS crosspoint enabling dynamic path assignment between upstream PHYs and downstream MAC interfaces. Use Value: Supports >1.5 Gbps per lane with 900-ps typical propagation delay, enabling deterministic latency control and reducing buffer depth requirements in cut-through forwarding.	Use Scenario: Multiplexing high-speed test patterns from multiple pattern generators to DUT inputs in automated test equipment (ATE) for SoC validation. IC Role / Device Role / Timing Role: Precision signal selector with independent per-output enable and low inter-channel crosstalk (<−50 dB). Use Value: Enables rapid test vector switching without signal corruption; 25-mV input hysteresis prevents false triggering on marginal edges during stress testing.

Wireless Base Station Clock Distribution

HDTV Video Routing

Use Scenario: Distributing synchronized OC-12 or 1.485-Gbps SMPTE 292 clocks across multiple RF transceiver modules in LTE/5G macro base stations.

IC Role / Device Role / Timing Role: Low-skew 4×4 LVDS crosspoint switch that routes master reference clocks to multiple downstream PLLs and ADC/DAC clock inputs.

Use Value: Maintains <150-ps channel skew across all four outputs, preserving setup/hold timing for multi-chip synchronization and reducing bit error rate in high-order QAM modulation.

Use Scenario: Switching uncompressed HD-SDI video streams between multiple camera inputs and display/encoder outputs in broadcast production switchers.

IC Role / Device Role / Timing Role: High-fidelity LVDS signal router handling 1.485-Gbps serial digital video with minimal jitter accumulation and no signal degradation.

Use Value: Delivers 65–110 ps peak-to-peak jitter at 1.5 Gbps, preserving eye opening for reliable 10-bit video sampling and avoiding frame sync loss.

High-Speed Network Router Fabric

Test Equipment Signal Multiplexing

Use Scenario: Interconnecting multiple line-card SerDes outputs to centralized packet processing ASICs in 10G/25G Ethernet routers.

IC Role / Device Role / Timing Role: Reconfigurable LVDS crosspoint enabling dynamic path assignment between upstream PHYs and downstream MAC interfaces.

Use Value: Supports >1.5 Gbps per lane with 900-ps typical propagation delay, enabling deterministic latency control and reducing buffer depth requirements in cut-through forwarding.

Use Scenario: Multiplexing high-speed test patterns from multiple pattern generators to DUT inputs in automated test equipment (ATE) for SoC validation.

IC Role / Device Role / Timing Role: Precision signal selector with independent per-output enable and low inter-channel crosstalk (<−50 dB).

Use Value: Enables rapid test vector switching without signal corruption; 25-mV input hysteresis prevents false triggering on marginal edges during stress testing.

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS crosspoint switching applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN65LVDT125ADBT	Includes integrated 110-Ω differential termination resistors on all inputs; higher input capacitance (0.6 pF vs. 0.4 pF typical for SN65LVDS125ADBT).	Better suited for space-constrained PCBs where external termination is impractical; requires tighter layout control due to higher capacitive loading.	Select SN65LVDT125ADBT when board area is premium and input termination can be omitted; otherwise, SN65LVDS125ADBT offers lower input loading and greater flexibility with external termination.
MAX9154ESE+	4×4 LVDS crosspoint with 2.5-Gbps capability, wider supply range (2.7–3.6 V), but higher ICC (175 mA typ) and larger SOIC-28 package.	Targeted at higher-speed test instrumentation and military avionics requiring extended temperature range (−40°C to +105°C).	Choose MAX9154ESE+ only if 2.5-Gbps headroom or extended temperature operation is required; SN65LVDS125ADBT provides superior skew performance and smaller TSSOP-38 footprint for telecom/datacom.

Compared with SN65LVDT125ADBT and MAX9154ESE+, the SN65LVDS125ADBT delivers the lowest channel skew (≤150 ps) in the smallest footprint (TSSOP-38), making it optimal for dense, timing-critical telecom routing where board space and deterministic latency outweigh termination integration or ultra-high-speed margin.

Availability

SN65LVDS125ADBT is available at Aetrix Electronics and suitable for wireless base station clock distribution, HDTV video switching, and high-speed network routing requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for SN65LVDS125ADBT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with decades of expertise in high-speed interface solutions.

The SN65LVDS125ADBT belongs to TI's LVDS interface product line, engineered specifically for deterministic, low-jitter signal routing in telecom infrastructure, broadcast video, and high-performance computing interconnects.

FAQ

What is the maximum data rate supported by the SN65LVDS125ADBT?

The SN65LVDS125ADBT supports signaling rates up to 1.5 Gbps per channel, validated with 223-1 PRBS patterns and confirmed via eye diagram analysis at 1.5 Gbps. This enables use in SMPTE 292 (1.485 Gbps) video and OC-12 (622 MHz) clock applications. Operation beyond 1.5 Gbps is not characterized or guaranteed.

Does the SN65LVDS125ADBT include on-chip termination resistors?

No, the SN65LVDS125ADBT does not integrate input or output termination resistors. It relies on external 100-Ω differential termination at the receiver end. In contrast, the pin-compatible SN65LVDT125ADBT variant includes 110-Ω integrated input terminations - a key functional distinction between the two parts.

Can the SN65LVDS125ADBT accept LVPECL or CML inputs?

Yes, the SN65LVDS125ADBT inputs are electrically compatible with LVPECL and CML signal levels in addition to LVDS, as explicitly stated in the datasheet. This eliminates the need for external level translators when interfacing with diverse SerDes sources in mixed-signal systems.

What is the function of the S10–S41 pins on the SN65LVDS125ADBT?

The S10–S41 pins are 2-bit binary control inputs that configure the source for each of the four outputs: S10/S11 selects the input for 1Y/1Z, S20/S21 for 2Y/2Z, etc. They implement non-blocking 4:1 multiplexing per output, allowing any input (1A/1B through 4A/4B) to be routed to any output independently.

Is the SN65LVDS125ADBT RoHS compliant and what is its MSL rating?

Yes, the SN65LVDS125ADBT is RoHS compliant and carries a moisture sensitivity level (MSL) rating of Level-2, with a peak reflow temperature of 260°C and a floor life of 1 year when stored at ≤30°C/60% RH. This is documented in TI's official packaging addendum for the DBT package.

SN65LVDS125ADBT Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 65LVDS

Package/Case:: 38-TFSOP (0.173", 4.40mm Width)

Packaging:: Bulk

Product Status:: Active

Type:: Crosspoint Switch

Circuit:: 1 x 4:4

Independent Circuits:: 1

Current - Output High, Low:: -

Voltage Supply Source:: Single Supply

Voltage - Supply:: 3V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 38-TSSOP

SN65LVDS125ADBT FAQ

1.How can I place an order for SN65LVDS125ADBT through Aetrix?

Please submit a Request for Quotation (RFQ) for SN65LVDS125ADBT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN65LVDS125ADBT reliable?

The price and inventory of SN65LVDS125ADBT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN65LVDS125ADBT is usually 5 days.

3.What payment methods are accepted for SN65LVDS125ADBT?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN65LVDS125ADBT transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN65LVDS125ADBT?

SN65LVDS125ADBT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN65LVDS125ADBT order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN65LVDS125ADBT?

For technical support, including SN65LVDS125ADBT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN65LVDS125ADBT requirements.

6.How does Aetrix verify that SN65LVDS125ADBT is sourced from the original manufacturer or authorized distributors?

All SN65LVDS125ADBT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN65LVDS125ADBT meets industry standards.

7.What is the process for return or replacement of SN65LVDS125ADBT?

All SN65LVDS125ADBT units undergo pre-shipment inspection (PSI). If there is an issue with SN65LVDS125ADBT, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN65LVDS125ADBT part is unused and in its original packaging.

Return procedure for SN65LVDS125ADBT:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…