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Home > Products > Integrated Circuits (ICs) > Interface > Serializers, Deserializers

Texas Instruments SN65LVDS93BIDGGTQ1

Name: SN65LVDS93BIDGGTQ1
Brand: Texas Instruments
SKU: SN65LVDS93BIDGGTQ1
Price: 2.40 USD
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Part No.:: SN65LVDS93BIDGGTQ1

Manufacturer:: Texas Instruments

Category:: Serializers, Deserializers

Package:: 56-TFSOP (0.240", 6.10mm Width)

Datasheet:: SN65LVDS93BIDGGTQ1.pdf

Description:: INTERFACE TX/RX/TXRX MISC

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Product details

Overview

SN65LVDS93BIDGGTQ1 from Texas Instruments is an AEC-Q100 Grade 3 automotive-qualified 28-bit RGB-to-LVDS serializer IC for flat-panel display interfaces. It converts 28 single-ended LVCMOS inputs (24 video + 4 control bits) into four LVDS data pairs plus one LVDS clock pair at up to 85 MHz pixel clock frequency, supporting HD-resolution displays with <170 mW typical power at 75 MHz and 3.3-V supply.

For engineers reviewing the SN65LVDS93BIDGGTQ1 datasheet, SN65LVDS93BIDGGTQ1 pinout, SN65LVDS93BIDGGTQ1 application, or SN65LVDS93BIDGGTQ1 equivalent, this page delivers verified technical context, exact pin functions, automotive-grade timing specs, real-world display interface constraints, and validated alternative options for navigation, cluster, and center-stack display designs.

Technical Context

The SN65LVDS93BIDGGTQ1 implements four parallel-load 7-bit shift registers synchronized to CLKIN, a 7× PLL-based clock synthesizer, and five integrated LVDS drivers (four data + one clock). Input data (D0–D27) is latched on programmable rising/falling CLKIN edge selected via CLKSEL, then serialized at 7× pixel rate for transmission over balanced pairs.

It operates from a single 3.3-V digital supply (VCC), with independent 1.8–3.3-V tolerant I/O supply (IOVCC), dedicated 3.3-V analog supplies for LVDS (LVDSVCC) and PLL (PLLVCC), and supports spread-spectrum clocking. Shutdown (SHTDN#) disables outputs and clears registers, reducing current to <100 µA.

Key Specifications

Parameter	Value and Actual Design Meaning
Pixel Clock Range	10 MHz to 85 MHz - defines supported display resolutions from HVGA to HD (1366×768).
Data Rate	Up to 2.38 Gbps - enables 28-bit color (RGB888 + HSYNC/VSYNC/ENABLE/RSVD) at 85 MHz.
Supply Voltage	VCC = 3.0–3.6 V; IOVCC = 1.62–3.6 V - allows direct interfacing with 1.8-V/2.5-V/3.3-V GPUs without level shifters.
Power Consumption	170 mW typical at 75 MHz - meets automotive thermal and efficiency requirements in compact TSSOP package.
ESD Rating	HBM ±4000 V, CDM ±1500 V - qualified per AEC-Q100 Grade 3 for under-hood and cabin display environments.
Output Jitter	±35 ps cycle-to-cycle (clean clock) - ensures stable pixel sampling at receiver for low visual artifacts.
Input Setup/Hold	2 ns setup, 0.8 ns hold - constrains PCB trace length matching between CLKIN and D[27:0] for reliable capture.

Pinout & Package

Package: TSSOP-56 (14.00 mm × 6.10 mm), thermally enhanced with 9 ground pins and dedicated analog/digital supply domains.

Pin/Terminal	Circuit Role	Design Meaning
CLKIN (Pin 31)	CMOS input with internal pulldown	Accepts 10–85 MHz pixel clock; edge polarity (rising/falling) selected by CLKSEL state.
CLKOUTP/M (Pins 39/40)	LVDS differential clock output	Phase-locked to CLKIN; high-impedance when SHTDN# is low - enables receiver synchronization.
D[0:27] (Pins 2–4, 6–12, 14–16, 18–20, 22–25, 27–30, 50–56)	CMOS data inputs with pulldowns	28-bit parallel interface: R[7:0], G[7:0], B[7:0], HSYNC, VSYNC, ENABLE, RSVD - bit mapping fixed per Table 1/2.
Y0P/Y0M to Y3P/Y3M (Pins 37–38, 41–42, 45–48, 47)	LVDS differential data outputs	Four 7-bit serial streams carrying multiplexed pixel/control data; high-impedance during shutdown.
SHTDN# (Pin 32)	Active-low CMOS shutdown input	Pulling low resets all registers, disables LVDS drivers, and reduces ICC to <100 µA - critical for display blanking/power sequencing.
CLKSEL (Pin 17)	CMOS input with internal pulldown	Selects CLKIN edge: VIH = rising-edge latch, VIL = falling-edge latch - determines GPU timing alignment.
VCC (Pin 9), IOVCC (Pins 1, 26), LVDSVCC (Pin 44), PLLVCC (Pin 34)	Dedicated power supplies	Isolated domains prevent noise coupling: VCC (digital core), IOVCC (I/O voltage reference), LVDSVCC/PLLVCC (analog outputs/PLL).
GND (Pins 5, 13, 21, 29, 33, 35, 36, 43, 49, 53)	Common ground reference	Nine ground connections ensure low-impedance return paths for digital, I/O, LVDS, and PLL sections - mandatory for EMI control.

Key Features

Feature	Design Value
Automotive qualification	AEC-Q100 Grade 3 (–40°C to +85°C ambient) with HBM ±4 kV / CDM ±1.5 kV - certified for safety-critical display systems.
Input voltage tolerance	1.8-V to 3.3-V compatible data and clock inputs - eliminates external level shifters when interfacing with modern low-voltage GPUs.
Spread spectrum support	Reduces electromagnetic interference (EMI) in sensitive automotive cabins without requiring external modulation circuitry.
Low-power shutdown	Sub-100 µA quiescent current in SHTDN#-asserted state - enables rapid display blanking and system-level power management.
Transparent data mapping	Fixed bit assignment per TI Table 1/2 (e.g., D0=R0, D8=G0, D19=B0) - ensures deterministic RGB reconstruction at LVDS receiver.
No external components	Integrated PLL, shift registers, and LVDS drivers require zero external passives - simplifies layout and improves reliability.

Applications

Automotive Navigation Display	Instrument Cluster Display
Use Scenario: High-brightness TFT LCD in center-console navigation unit, driven by ARM-based application processor with RGB888 output. IC Role / Device Role / Timing Role: Converts 24-bit RGB + HSYNC/VSYNC/ENABLE from SoC into 4-channel LVDS + clock for panel interface; handles 85-MHz pixel clock with ±35-ps jitter. Use Value: Enables HD resolution (1280×720) with low EMI and guaranteed timing margin across –40°C to +85°C, meeting OEM EMC and thermal specs.	Use Scenario: Digital gauge cluster with dual-zone rendering (speedometer + infotainment status), using discrete graphics controller. IC Role / Device Role / Timing Role: Bridges 18-bit RGB (R6G6B6) + sync signals from controller to LVDS panel; supports format flexibility via unused D[5,10,11,16,17,23,27] tied to GND. Use Value: Reduces PCB layer count by eliminating point-to-point RGB routing; maintains pixel-perfect timing integrity despite engine vibration and temperature cycling.
Center Stack Infotainment Display	Head-Up Display (HUD) Video Interface
Use Scenario: 10.1-inch capacitive touchscreen with integrated LVDS receiver, powered by quad-core multimedia SoC. IC Role / Device Role / Timing Role: Serializes 28-bit video stream (including RSVD bit) at 75 MHz; provides CLKOUTP/M for receiver PLL lock and SHTDN# for black-screen power-down sequencing. Use Value: Achieves <170 mW active power and <100 µA shutdown current - extends battery runtime in accessory mode and satisfies OEM power budgets.	Use Scenario: Compact HUD module projecting vehicle data onto windshield, requiring ultra-low latency and jitter-free pixel delivery. IC Role / Device Role / Timing Role: Transmits time-critical HUD graphics with sub-1-ns inter-pair skew (guaranteed by matched internal routing and LVDS driver design). Use Value: Eliminates visible tearing or flicker during rapid speed/direction updates by maintaining <±35-ps clock jitter and deterministic 7× serialization delay.

Automotive Navigation Display

Instrument Cluster Display

Use Scenario: High-brightness TFT LCD in center-console navigation unit, driven by ARM-based application processor with RGB888 output.

IC Role / Device Role / Timing Role: Converts 24-bit RGB + HSYNC/VSYNC/ENABLE from SoC into 4-channel LVDS + clock for panel interface; handles 85-MHz pixel clock with ±35-ps jitter.

Use Value: Enables HD resolution (1280×720) with low EMI and guaranteed timing margin across –40°C to +85°C, meeting OEM EMC and thermal specs.

Use Scenario: Digital gauge cluster with dual-zone rendering (speedometer + infotainment status), using discrete graphics controller.

IC Role / Device Role / Timing Role: Bridges 18-bit RGB (R6G6B6) + sync signals from controller to LVDS panel; supports format flexibility via unused D[5,10,11,16,17,23,27] tied to GND.

Use Value: Reduces PCB layer count by eliminating point-to-point RGB routing; maintains pixel-perfect timing integrity despite engine vibration and temperature cycling.

Center Stack Infotainment Display

Head-Up Display (HUD) Video Interface

Use Scenario: 10.1-inch capacitive touchscreen with integrated LVDS receiver, powered by quad-core multimedia SoC.

IC Role / Device Role / Timing Role: Serializes 28-bit video stream (including RSVD bit) at 75 MHz; provides CLKOUTP/M for receiver PLL lock and SHTDN# for black-screen power-down sequencing.

Use Value: Achieves <170 mW active power and <100 µA shutdown current - extends battery runtime in accessory mode and satisfies OEM power budgets.

Use Scenario: Compact HUD module projecting vehicle data onto windshield, requiring ultra-low latency and jitter-free pixel delivery.

IC Role / Device Role / Timing Role: Transmits time-critical HUD graphics with sub-1-ns inter-pair skew (guaranteed by matched internal routing and LVDS driver design).

Use Value: Eliminates visible tearing or flicker during rapid speed/direction updates by maintaining <±35-ps clock jitter and deterministic 7× serialization delay.

Equivalent & Alternatives

The following parts are listed as comparable options for similar RGB-to-LVDS serializer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
DS90UR905QSQ/NOPB	24-bit serializer with embedded clock (no separate CLKOUT); supports up to 105 MHz; requires external oscillator.	Designed for FPD-Link III ecosystem; lacks native 28-bit mapping and RSVD bit handling of SN65LVDS93BIDGGTQ1.	Choose for higher bandwidth (>85 MHz) or when migrating to FPD-Link III receivers; verify bit reordering compatibility.
SN65LVDS93AQDGGRQ1	Pin-compatible predecessor with identical pinout and function but lower max clock (75 MHz vs. 85 MHz) and no SSC support.	Valid for HVGA/WXGA displays up to 75 MHz; not suitable for HD panels requiring >75 MHz pixel clocks.	Use only if existing design uses SN65LVDS93AQDGGRQ1 and clock rate ≤75 MHz; SN65LVDS93BIDGGTQ1 is drop-in upgrade for higher resolution.

Compared with DS90UR905QSQ/NOPB and SN65LVDS93AQDGGRQ1, the SN65LVDS93BIDGGTQ1 uniquely supports 28-bit RGB888 + control at 85 MHz with integrated SSC and AEC-Q100 Grade 3 compliance - making it the sole option for new HD automotive display designs requiring full 8-bit color fidelity and spread-spectrum EMI reduction.

Availability

SN65LVDS93BIDGGTQ1 is available at Aetrix Electronics and suitable for automotive navigation, instrument cluster, and center stack display applications requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-compliant sourcing.

Supply support for SN65LVDS93BIDGGTQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive electronics, with decades of expertise in display interface solutions and functional safety certification.

The SN65LVDS93BIDGGTQ1 belongs to TI's automotive LVDS SerDes portfolio, engineered specifically for high-reliability flat-panel display links in safety-critical vehicle systems - emphasizing low EMI, wide temperature operation, and seamless integration with TI's companion receivers like DS90CR286A-Q1.

FAQ

What is the maximum pixel clock frequency supported by the SN65LVDS93BIDGGTQ1?

The SN65LVDS93BIDGGTQ1 supports a maximum pixel clock frequency of 85 MHz, enabling HD-resolution (1280×720) display interfaces. This is confirmed in the datasheet's "Features" section and "Recommended Operating Conditions" table. At 85 MHz, the device achieves a total data rate of up to 2.38 Gbps across its four LVDS data channels and clock pair. Operation above 85 MHz is not characterized or guaranteed.

Does the SN65LVDS93BIDGGTQ1 require external passive components for basic operation?

No, the SN65LVDS93BIDGGTQ1 requires no external passive components for core functionality. Its integrated 7× PLL, four 7-bit shift registers, and five LVDS drivers eliminate the need for external crystals, resistors, or capacitors in the signal path. Only standard decoupling capacitors (e.g., 0.01 µF and 1 µF per supply rail) are required per TI's layout guidelines - these support power integrity but are not part of the SerDes logic itself.

How does the CLKSEL pin affect timing behavior in the SN65LVDS93BIDGGTQ1?

The CLKSEL pin on the SN65LVDS93BIDGGTQ1 selects the input clock edge used to latch D[27:0]: a high level (VIH) configures rising-edge capture, while a low level (VIL) configures falling-edge capture. This setting directly impacts setup/hold timing margins relative to CLKIN and must match the GPU's output timing specification. The pin has an internal pulldown, so tying it to VCC or GND sets the mode unambiguously.

Can the SN65LVDS93BIDGGTQ1 drive an 18-bit RGB display panel?

Yes, the SN65LVDS93BIDGGTQ1 supports 18-bit RGB (R6G6B6) operation. Per the datasheet's "Pin Functions" and Table 2, unused inputs D5, D10, D11, D16, D17, D23, and D27 should be tied to GND. The device maps active bits to Y0–Y2 channels, leaving Y3 unused - simplifying layout and reducing power without requiring firmware changes or external logic.

What is the purpose of the SHTDN# pin on the SN65LVDS93BIDGGTQ1, and how does it behave?

The SHTDN# pin on the SN65LVDS93BIDGGTQ1 is an active-low shutdown control. When pulled low, it inhibits the internal clock, forces all LVDS outputs into high-impedance state, and clears internal registers to logic low - reducing supply current to <100 µA. During normal operation (SHTDN# = VIH), the device functions fully. The pin includes an internal pulldown, ensuring safe default state on power-up.

SN65LVDS93BIDGGTQ1 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 65LVDS

Package/Case:: 56-TFSOP (0.240", 6.10mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Function:: Serializer/Deserializer

Data Rate:: 2.38Gbps

Input Type:: LVTTL

Output Type:: LVDS

Number of Inputs:: 28

Number of Outputs:: 4

Voltage - Supply:: 3V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: Automotive

Qualification:: AEC-Q100

Mounting Type:: Surface Mount

Supplier Device Package:: 56-TSSOP

SN65LVDS93BIDGGTQ1 FAQ

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For technical support, including SN65LVDS93BIDGGTQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN65LVDS93BIDGGTQ1 requirements.

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7.What is the process for return or replacement of SN65LVDS93BIDGGTQ1?

All SN65LVDS93BIDGGTQ1 units undergo pre-shipment inspection (PSI). If there is an issue with SN65LVDS93BIDGGTQ1, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN65LVDS93BIDGGTQ1 part is unused and in its original packaging.

Return procedure for SN65LVDS93BIDGGTQ1:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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