Texas Instruments SN65LVDS95DGGREP

Overview

SN65LVDS95DGGREP from Texas Instruments is a 21:3 LVDS serializer IC that converts 21-bit LVTTL parallel data and clock into three LVDS serial streams plus one LVDS clock output, operating at up to 1.36 Gbps aggregate throughput with 3.3-V supply, 250-mW typical power, and industrial −40°C to 85°C temperature range. It enables point-to-point high-speed subsystem interconnects in backplane and board-to-board applications.

For engineers reviewing the SN65LVDS95DGGREP datasheet, SN65LVDS95DGGREP pinout, SN65LVDS95DGGREP application, or SN65LVDS95DGGREP equivalent, key selection criteria include its 21-bit parallel-to-3×LVDS serialization ratio, 20–68 MHz PLL-compatible input clock range, 5-V-tolerant inputs, 6-kV HBM ESD tolerance on bus pins, and TSSOP-48 package with 20-mil pitch.

Technical Context

The SN65LVDS95DGGREP integrates three 7-bit parallel-load shift registers, a 7× clock synthesizer/PLL, and four LVDS line drivers - enabling synchronous serialization of D0–D20 and CLKIN into Y0P/Y0M, Y1P/Y1M, Y2P/Y2M, and CLKOUTP/CLKOUTM outputs. Its rising-edge-triggered inputs and internal register clearing on SHTDN low ensure deterministic timing alignment.

No external components are required for PLL operation; the device supports transparent data transmission with minimal control - only SHTDN active-low shutdown is user-configurable. Input clock jitter tolerance is specified at ±50 ps, and output skew across serialized bits is limited to ±0.2 ns.

Key Specifications

Pinout & Package

Packaged in a 48-pin Thin Shrink Small-Outline Package (TSSOP-DGG) with 20-mil terminal pitch, lead-free (NiPdAu) finish, and moisture sensitivity level 1 (260°C peak reflow).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS serializer applications.

Compared with SN65LVDS95DGG and SN65LVDS93DGG, the SN65LVDS95DGGREP uniquely combines 21:3 compression, industrial temperature qualification with full DMS pedigree, active-low shutdown, and pin-compatibility with legacy DS90CR215-based designs - making it optimal for long-lifecycle, EMI-sensitive industrial subsystems.

Availability

SN65LVDS95DGGREP is available at Aetrix Electronics and suitable for industrial backplane extensions, virtual backplane transceivers, high-density board-to-board interconnects, and parity-protected bus links requiring stable component supply across extended product lifecycles.

Supply support for SN65LVDS95DGGREP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 90 years of innovation in high-reliability electronic components.

The SN65LVDS95DGGREP belongs to TI's LVDS SerDes product line, designed specifically for noise-immune, high-speed parallel bus extension in industrial, test equipment, and modular computing systems where EMI reduction and PCB trace minimization are critical.

FAQ

What is the primary function of the SN65LVDS95DGGREP in a signal chain?

The SN65LVDS95DGGREP functions as a 21-bit parallel-to-LVDS serializer, converting 21 LVTTL data bits and one clock signal into three differential LVDS data streams plus one LVDS clock output. It enables high-speed, low-EMI point-to-point communication between subsystems, and is commonly paired with the SN65LVDS96 receiver. Its 7× internal clock multiplication allows efficient serialization without external PLL components.

Does the SN65LVDS95DGGREP require external passive components for PLL operation?

No, the SN65LVDS95DGGREP requires no external components for PLL operation. Its integrated 7× clock synthesizer locks to the 20–68 MHz CLKIN input and generates the high-frequency serial clock internally. This eliminates the need for external loop filters, capacitors, or resistors - simplifying schematic design and reducing bill-of-materials cost compared to discrete PLL solutions.

What is the purpose of the SHTDN pin on the SN65LVDS95DGGREP?

The SHTDN pin on the SN65LVDS95DGGREP is an active-low shutdown control. When pulled low, it clears all internal shift registers to logic low and disables the LVDS output drivers, reducing total power consumption to less than 1 mW. This feature enables dynamic power gating during idle periods in battery-sensitive or thermally constrained applications, while preserving fast re-enable timing (1 ms enable time).

Can the SN65LVDS95DGGREP interface directly with 5-V TTL logic?

Yes, the SN65LVDS95DGGREP features 5-V-tolerant parallel data inputs (D0–D20) and CLKIN, allowing direct connection to standard 5-V TTL or CMOS logic without level-shifting circuitry. Input thresholds are defined at VIH = 2 V and VIL = 0.8 V, and absolute maximum input voltage is rated to 5.5 V - ensuring robust interoperability with legacy digital interfaces while operating from a 3.3-V supply.

How does the SN65LVDS95DGGREP manage timing skew between serialized data lanes?

The SN65LVDS95DGGREP maintains tight inter-lane timing alignment through synchronous loading and deterministic 7-bit slicing: all 21 data bits are latched on the same CLKIN rising edge, then shifted out with precisely timed delays (t0–t6 spaced at 1/7 of the input clock period). Output skew between any two serialized bits is guaranteed to be within ±0.2 ns, enabling reliable clock-data recovery at the receiver without complex deskew logic.