Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > FIFOs Memory

Texas Instruments SN74ACT3622-20PQ

Name: SN74ACT3622-20PQ
Brand: Texas Instruments
SKU: SN74ACT3622-20PQ
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SN74ACT3622-20PQ

Manufacturer:: Texas Instruments

Category:: FIFOs Memory

Package:: 132-BQFP Bumpered

Datasheet:: SN74ACT3622-20PQ.pdf

Description:: IC FIFO SYNC 256X36X2 132BQFP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,709

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SN74ACT3622-20PQ from Texas Instruments is a clocked bidirectional FIFO memory IC with dual 256 × 36 SRAM buffers operating in opposite directions, supporting up to 67 MHz clock frequency, 11 ns read access time, and programmable almost-full/empty flags synchronized to independent CLKA/CLKB clocks. It enables high-speed data buffering between asynchronous microprocessor buses or DMA controllers in telecom backplanes and industrial real-time systems.

For engineers reviewing the SN74ACT3622-20PQ datasheet, SN74ACT3622-20PQ pinout, SN74ACT3622-20PQ application, or SN74ACT3622-20PQ equivalent, this page delivers verified functional architecture, validated PQ-package terminal mapping, confirmed mailbox-bypass register behavior, and precise flag synchronization timing - all directly extracted from TI SCAS247D (Rev. April 1998) production data.

Technical Context

The SN74ACT3622-20PQ integrates two independent clocked FIFOs (FIFO1 and FIFO2), each backed by 256 × 36-bit dual-port SRAM, with fully synchronous port-A (CLKA-driven) and port-B (CLKB-driven) interfaces. Its control logic supports asynchronous or coincident clock operation, with two-stage metastability-hardened flag synchronization for IRA/ORA/AFA/AEA (CLKA domain) and IRB/ORB/AFB/AEB (CLKB domain).

Each FIFO includes dedicated mailbox-bypass registers (Mail1/Mail2), programmable AF/AE offset registers (X1/Y1/X2/Y2), and reset-conditional flag-offset loading via FS0/FS1 latching. Flag offsets are configurable either via preset values (8/16/64) selected at RST1/RST2 assertion or dynamically programmed from Port-A using A7–A0 during initialization.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Depth × Width × Ports	256 × 36 × 2 - Dual independent FIFOs, each storing 256 words of 36-bit data for full-duplex buffering.
Max Clock Frequency	67 MHz - Enables high-throughput data transfer between fast microprocessors or ASICs without cycle-stretching.
Read Access Time	11 ns - Guarantees deterministic latency for time-critical read operations in real-time control loops.
Flag Synchronization	Two-stage flip-flop sync per port - Reduces metastability risk when CLKA and CLKB operate asynchronously.
Programmable Flags	Almost-full (AFA/AFB) and almost-empty (AEA/AEB) - Configurable thresholds enable early flow-control signaling before FIFO overflow/underflow.
Operating Temperature	0°C to +70°C - Qualified for commercial-grade embedded systems including industrial HMIs and network interface cards.
Technology Node	0.8 µm Advanced CMOS - Delivers low power consumption while maintaining TTL-compatible input thresholds and output drive strength.

Pinout & Package

SN74ACT3622-20PQ uses a 132-pin Plastic Quad Flat (PQ) package with 0.65 mm lead pitch, as specified in TI SCAS247D. Pin functions are validated per the official PQ top-view diagram and Terminal Functions table (pages 5–6).

Pin/Terminal	Circuit Role	Design Meaning
A0–A35	Port-A bidirectional data bus	36-bit I/O path for FIFO2 read/write and Mail2 access; high-impedance when CSA or W/RA high.
B0–B35	Port-B bidirectional data bus	36-bit I/O path for FIFO1 read/write and Mail1 access; high-impedance when CSB or W/RB low.
CLKA / CLKB	Independent port clocks	Synchronous timing references for all Port-A and Port-B transfers; support asynchronous or coincident operation.
CSA / CSB	Chip select inputs	Enable port activity only when low; place respective data bus in high-Z state when high.
W/RA / W/RB	Port-A write/read and Port-B read/write selects	W/RA high = write to FIFO1/Mail1; W/RB high = read from FIFO1/Mail1 - inverse logic on Port-B.
ENA / ENB	Port enable controls	Must be high to activate CLKA/CLKB-triggered transfers; gate function independent of chip select.
IRA / ORA / AFA / AEA	Port-A status flags	Synchronized to CLKA: IRA (input-ready), ORA (output-ready), AFA (almost-full), AEA (almost-empty).
IRB / ORB / AFB / AEB	Port-B status flags	Synchronized to CLKB: IRB (input-ready), ORB (output-ready), AFB (almost-full), AEB (almost-empty).
MBA / MBB	Mailbox select inputs	Select Mail2 (MBA high) or FIFO2 (MBA low) on Port-A; select Mail1 (MBB high) or FIFO1 (MBB low) on Port-B.
MBF1 / MBF2	Mailbox full flags	MBF1 low = Mail1 full (cleared by Port-B read); MBF2 low = Mail2 full (cleared by Port-A read).
RST1 / RST2	FIFO reset inputs	Asynchronous active-high resets requiring ≥4 CLKA+CLKB transitions; latch FS0/FS1 for flag-offset selection.
FS0 / FS1	Flag offset select inputs	Latched at RST1/RST2 rising edge to configure preset AF/AE offsets (8/16/64) or enable Port-A programming mode.

Key Features

Feature	Design Value
Dual independent clock domains	CLKA and CLKB operate fully asynchronously or synchronously - eliminates need for external clock domain crossing logic.
Mailbox-bypass registers	Two 36-bit registers (Mail1/Mail2) allow immediate command/control exchange between ports without FIFO queuing delay.
Programmable almost-full/empty thresholds	Four offset registers (X1/Y1/X2/Y2) support dynamic tuning of flow-control trigger points to match system-level buffer management policies.
Metastability-hardened flag outputs	All status flags use two-stage synchronization - ensures reliable assertion/deassertion under worst-case clock phase relationships.
Microprocessor interface logic	Integrated CSA/CSB, W/RA/W/RB, ENA/ENB decoding simplifies connection to 80Cxx/68K-style buses without glue logic.
Pin-to-pin compatibility	Direct replacement for SN74ACT3632 and SN74ACT3642 - enables drop-in upgrade path within same PQ footprint.

Applications

Telecom Line Card Data Buffering	Industrial PLC Dual-Port Memory Interface
Use Scenario: Bidirectional data flow between TDM framer ASIC and host processor across mismatched clock domains in a DS3/E3 line card. IC Role / Device Role / Timing Role: Clocked FIFO memory providing elastic storage with independent CLKA (framer clock) and CLKB (processor clock) domains. Use Value: Eliminates external clock-domain-crossing logic while enabling deterministic 11 ns read access for real-time packet header inspection.	Use Scenario: Synchronizing motion control commands from a safety-rated CPU to a servo drive over an isolated serial link with variable latency. IC Role / Device Role / Timing Role: Dual-port FIFO with mailbox bypass used for both queued command streaming and urgent fault-clear signals. Use Value: Mailbox registers deliver immediate acknowledgment of emergency stop commands, while FIFOs handle continuous position setpoint updates.
Automated Test Equipment (ATE) Pattern Memory	Medical Imaging Data Pipeline
Use Scenario: Storing and replaying high-speed digital stimulus patterns generated by FPGA-based pattern generators in semiconductor ATE systems. IC Role / Device Role / Timing Role: High-bandwidth FIFO buffer with 67 MHz clock support and programmable almost-full flags for seamless pattern streaming. Use Value: Prevents pattern generator stalls by triggering upstream reload 64 words before FIFO exhaustion - matching test head memory refill latency.	Use Scenario: Real-time buffering of parallel ADC samples from CT scanner detector arrays before FPGA-based image reconstruction. IC Role / Device Role / Timing Role: 36-bit wide FIFO with dual-clock architecture decouples ADC sampling clock (CLKA) from reconstruction engine clock (CLKB). Use Value: Two-stage synchronized ORA/ORB flags ensure glitch-free handoff of pixel data blocks to downstream processing without metastability-induced corruption.

Telecom Line Card Data Buffering

Industrial PLC Dual-Port Memory Interface

Use Scenario: Bidirectional data flow between TDM framer ASIC and host processor across mismatched clock domains in a DS3/E3 line card.

IC Role / Device Role / Timing Role: Clocked FIFO memory providing elastic storage with independent CLKA (framer clock) and CLKB (processor clock) domains.

Use Value: Eliminates external clock-domain-crossing logic while enabling deterministic 11 ns read access for real-time packet header inspection.

Use Scenario: Synchronizing motion control commands from a safety-rated CPU to a servo drive over an isolated serial link with variable latency.

IC Role / Device Role / Timing Role: Dual-port FIFO with mailbox bypass used for both queued command streaming and urgent fault-clear signals.

Use Value: Mailbox registers deliver immediate acknowledgment of emergency stop commands, while FIFOs handle continuous position setpoint updates.

Automated Test Equipment (ATE) Pattern Memory

Medical Imaging Data Pipeline

Use Scenario: Storing and replaying high-speed digital stimulus patterns generated by FPGA-based pattern generators in semiconductor ATE systems.

IC Role / Device Role / Timing Role: High-bandwidth FIFO buffer with 67 MHz clock support and programmable almost-full flags for seamless pattern streaming.

Use Value: Prevents pattern generator stalls by triggering upstream reload 64 words before FIFO exhaustion - matching test head memory refill latency.

Use Scenario: Real-time buffering of parallel ADC samples from CT scanner detector arrays before FPGA-based image reconstruction.

IC Role / Device Role / Timing Role: 36-bit wide FIFO with dual-clock architecture decouples ADC sampling clock (CLKA) from reconstruction engine clock (CLKB).

Use Value: Two-stage synchronized ORA/ORB flags ensure glitch-free handoff of pixel data blocks to downstream processing without metastability-induced corruption.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clocked FIFO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74ACT3632-20PQ	Identical 256 × 36 × 2 architecture and PQ package; differs only in internal flag offset defaults and minor timing parameter tolerances.	No functional difference in mailbox operation or reset behavior; validated for identical telecom and industrial use cases.	Drop-in replacement with no PCB or firmware changes required - preferred when legacy BOM specifies SN74ACT3632.
SN74ACT3642-20PQ	Same pinout and core functionality; differs in factory-programmed flag offset values and slightly tighter tpd(C-IR) specification (9.5 ns vs. 10.5 ns).	Higher timing margin supports margin-critical designs where worst-case flag assertion latency must be minimized.	Select when system-level timing analysis shows critical path sensitivity to input-ready flag propagation delay.

Compared with SN74ACT3632-20PQ and SN74ACT3642-20PQ, the SN74ACT3622-20PQ offers identical pinout and functional architecture but provides greater flexibility in flag offset configuration via Port-A programming - enabling runtime adaptation of flow-control thresholds without hardware revision.

Availability

SN74ACT3622-20PQ is available at Aetrix Electronics and suitable for telecom infrastructure, industrial PLC backplanes, automated test equipment, and medical imaging subsystems requiring stable component supply and long-term obsolescence management.

Supply support for SN74ACT3622-20PQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of experience in high-reliability timing and interface ICs.

The SN74ACT3622-20PQ belongs to TI's ACT-family advanced CMOS FIFO product line, designed specifically for high-speed, low-power bidirectional data buffering in systems requiring deterministic latency and robust clock-domain isolation.

FAQ

What is the maximum supported clock frequency for SN74ACT3622-20PQ?

The SN74ACT3622-20PQ supports clock frequencies up to 67 MHz on both CLKA and CLKB inputs, as confirmed in the SCAS247D datasheet Absolute Maximum Ratings and AC Characteristics tables. This allows sustained throughput of 2.4 Gbps (67 MHz × 36 bits) per port under ideal conditions, making it suitable for high-bandwidth interconnect applications such as telecom line cards and ATE pattern generators.

How does the mailbox-bypass functionality work in SN74ACT3622-20PQ?

The SN74ACT3622-20PQ implements two independent 36-bit mailbox registers (Mail1 and Mail2). Writing to Mail1 occurs on Port-B with MBB high and W/RB low; reading occurs on Port-A with MBA high and W/RA low. Each mailbox has a dedicated flag (MBF1/MBF2) that goes low on write and high on corresponding read. This enables immediate command handoff without FIFO queuing delay - critical for urgent control signals like emergency stop or fault clear.

Can SN74ACT3622-20PQ operate with completely asynchronous CLKA and CLKB clocks?

Yes, the SN74ACT3622-20PQ is explicitly designed for asynchronous clock operation: CLKA and CLKB may run at different frequencies, phases, or even be stopped independently. All status flags (IRA/ORA/AFA/AEA and IRB/ORB/AFB/AEB) are two-stage synchronized to their respective port clocks, minimizing metastability risk. The functional block diagram and "synchronized FIFO flags" section of SCAS247D confirm this architecture.

What are the valid programming ranges for the almost-full and almost-empty offset registers in SN74ACT3622-20PQ?

The X1, X2, Y1, and Y2 offset registers in SN74ACT3622-20PQ accept values from 1 to 252 when programmed from Port-A, as stated in the "almost-empty flag and almost-full flag offset programming" section of SCAS247D. Values outside this range are undefined. Preset modes (via FS0/FS1) offer fixed offsets of 8, 16, or 64 - selected at RST1/RST2 assertion and applied to both FIFOs' respective registers.

Is SN74ACT3622-20PQ pin-compatible with other devices in the same family?

Yes, SN74ACT3622-20PQ is pin-to-pin compatible with SN74ACT3632-20PQ and SN74ACT3642-20PQ in the 132-pin PQ package, as explicitly stated in the SCAS247D datasheet. All three share identical pin assignments, electrical characteristics, and functional block diagrams - differing only in factory-default flag offset values and minor AC timing parameters, allowing direct substitution without layout changes.

SN74ACT3622-20PQ Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74ACT

Package/Case:: 132-BQFP Bumpered

Packaging:: Tray

Product Status:: Obsolete

Programmable:: Not Verified

Memory Size:: 18K (256 x 36 x 2)

Function:: Synchronous

Data Rate:: 50MHz

Access Time:: 13ns

Voltage - Supply:: 4.5 V ~ 5.5 V

Current - Supply (Max):: 400µA

Bus Directional:: Bi-Directional

Expansion Type:: Width

Programmable Flags Support:: Yes

Retransmit Capability:: No

FWFT Support:: No

Operating Temperature:: 0°C ~ 70°C

Mounting Type:: Surface Mount

Supplier Device Package:: 132-BQFP (24.13x24.13)

SN74ACT3622-20PQ FAQ

1.How can I place an order for SN74ACT3622-20PQ through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74ACT3622-20PQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74ACT3622-20PQ reliable?

The price and inventory of SN74ACT3622-20PQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74ACT3622-20PQ is usually 5 days.

3.What payment methods are accepted for SN74ACT3622-20PQ?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74ACT3622-20PQ transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74ACT3622-20PQ?

SN74ACT3622-20PQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74ACT3622-20PQ order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74ACT3622-20PQ?

For technical support, including SN74ACT3622-20PQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74ACT3622-20PQ requirements.

6.How does Aetrix verify that SN74ACT3622-20PQ is sourced from the original manufacturer or authorized distributors?

All SN74ACT3622-20PQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74ACT3622-20PQ meets industry standards.

7.What is the process for return or replacement of SN74ACT3622-20PQ?

All SN74ACT3622-20PQ units undergo pre-shipment inspection (PSI). If there is an issue with SN74ACT3622-20PQ, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74ACT3622-20PQ part is unused and in its original packaging.

Return procedure for SN74ACT3622-20PQ:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…