Texas Instruments SN74AHC123AD
- Part No.:
- SN74AHC123AD
- Manufacturer:
- Texas Instruments
- Category:
- Multivibrators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74AHC123AD.pdf
- Description:
- IC MULTIVIBRATOR 7.5NS 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,310
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74AHC123AD from Texas Instruments is a dual retriggerable monostable multivibrator IC operating from 2 V to 5.5 V, featuring Schmitt-trigger inputs on A, B, and CLR for noise immunity, edge-triggered operation (rising or falling), and programmable output pulse duration via external R/C networks. It delivers glitch-free power-up reset and supports overriding clear to terminate pulses early - used in timing control, debouncing, and pulse shaping circuits.
For engineers reviewing the SN74AHC123AD datasheet, SN74AHC123AD pinout, SN74AHC123AD application, or SN74AHC123AD equivalent, this page provides verified functional identity, SOIC-16 package mapping, confirmed timing parameters (e.g., tPLH ≤ 14 ns at 5 V), real-world retriggering behavior (tMIR ≈ 0.3 × tw), and validated alternative options for monostable timing functions.
Technical Context
The SN74AHC123AD implements two independent monostable multivibrators, each with three trigger modes: A-low/B-high, A-high/B-low, or A-low/B-high/CLR-high. Pulse width is set externally by Rext and Cext, with K-factor scaling dependent on Cext value (K = 1.0 if ≥1000 pF).
Each channel supports retriggering during active output to extend pulse duration, and CLR can force immediate low-state termination. Inputs use Schmitt-trigger circuitry with hysteresis sufficient for slow transitions, and outputs are fully buffered CMOS with rail-to-rail swing and ±8 mA drive capability at 5 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2 V to 5.5 V - enables interoperability across 3.3 V and 5 V logic systems without level shifters. |
| Output Drive | ±8 mA at 5 V - sufficient to directly drive TTL loads or small LEDs without external buffers. |
| Propagation Delay | tPLH/tPHL ≤ 14 ns at 5 V, CL = 50 pF - supports timing-critical applications up to ~35 MHz toggle rate. |
| Pulse Duration Range | 90 ns to >1 ms - programmable via Rext (1 kΩ–10 kΩ) and Cext (28 pF–0.1 μF) combinations. |
| Input Hysteresis | Typical ΔV = 0.5 V at 3.3 V - rejects noise on slow-rising/falling signals like mechanical switch bounce. |
| Power-Up State | Q = L, Q̅ = H - deterministic initial condition eliminates need for external reset circuitry. |
| Quiescent Current | 40 μA max at 5.5 V - suitable for low-power standby timing functions in battery-operated systems. |
Pinout & Package
SN74AHC123AD is supplied in a 16-pin SOIC (D) package measuring 9.00 mm × 6.00 mm (body: 9.00 mm × 3.90 mm), with standard 1.27 mm pitch and gull-wing leads. Thermal resistance RθJA = 73 °C/W enables operation up to +85 °C ambient without forced airflow.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 A | Channel 1 trigger input (falling-edge active when 1B = H) | Enables edge-selectable triggering; must be held low for alternate modes. |
| 2 B | Channel 1 trigger input (rising-edge active when 1A = L) | Complements A input; high-level hold required for gated operation. |
| 3 1CLR | Channel 1 asynchronous clear input | Rising-edge triggered; overrides active output pulse when asserted. |
| 4 1Q | Channel 1 non-inverted output | CMOS-compatible output; drives loads up to ±8 mA at 5 V. |
| 5 2Q | Channel 2 non-inverted output | Independent timing channel; identical electrical specs to 1Q. |
| 6 2Cext | Channel 2 external capacitor negative terminal | Connects to ground side of timing capacitor; no internal connection. |
| 7 2Rext/Cext | Channel 2 R/C junction node | Connects external resistor to VCC and capacitor to 2Cext for pulse-width programming. |
| 8 GND | Ground reference | Primary return path; requires local 0.1 μF bypass capacitor. |
| 9 2A | Channel 2 trigger input (falling-edge active when 2B = H) | Functionally identical to Pin 1 but for second channel. |
| 10 2B | Channel 2 trigger input (rising-edge active when 2A = L) | Functionally identical to Pin 2 but for second channel. |
| 11 2CLR | Channel 2 asynchronous clear input | Functionally identical to Pin 3 but for second channel. |
| 12 2Q̅ | Channel 2 inverted output | Complementary to 2Q; matches 1Q̅ in timing and drive strength. |
| 13 1Q̅ | Channel 1 inverted output | Complementary to 1Q; enables direct logic inversion without extra gate. |
| 14 1Cext | Channel 1 external capacitor negative terminal | Ground-side connection point for Channel 1 timing capacitor. |
| 15 1Rext/Cext | Channel 1 R/C junction node | Same function as Pin 7, but for Channel 1 timing network. |
| 16 VCC | Positive supply | Must be decoupled locally; supports 2–5.5 V operation with stable regulation. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent monostables | Two fully isolated timing channels share only VCC/GND - enables synchronized or independent pulse generation. |
| Retriggerable architecture | Extends active output pulse on new trigger before timeout - eliminates need for external one-shot chaining logic. |
| Three-input trigger logic | Supports A-only, B-only, or A+B+CLR combinations - increases flexibility in system-level edge detection schemes. |
| Glitch-free power-up reset | Outputs settle deterministically to Q = L / Q̅ = H at power-on - removes requirement for external POR circuitry. |
| Schmitt-trigger inputs | Hysteresis ≥0.5 V at 3.3 V - suppresses chatter from noisy or slow-switching sources like pushbuttons or sensors. |
Applications
| Industrial Pushbutton Debouncing | Serial Data Pulse Stretching |
|---|---|
|
Use Scenario: Mechanical panel switches generate multiple contact bounces lasting 5–20 ms, causing false interrupts in microcontroller GPIOs. IC Role / Device Role / Timing Role: SN74AHC123AD acts as hardware debouncer: each switch connects to A/B inputs, and Q output feeds clean, single-pulse signal to MCU. Use Value: Eliminates firmware debounce loops; guarantees <100 ns jitter between bounce rejection and output stabilization using 10 kΩ/100 nF R/C network. |
Use Scenario: Low-duty-cycle UART or SPI data pulses require minimum pulse width compliance for reliable receiver sampling. IC Role / Device Role / Timing Role: SN74AHC123AD stretches narrow incoming data edges (e.g., 50 ns) to ≥500 ns using fixed R/C timing. Use Value: Ensures robust clock/data setup/hold margins at receivers without altering source timing or adding FPGA logic. |
| Motor Control Fault Pulse Extension | Test Equipment Trigger Synchronization |
|
Use Scenario: Overcurrent protection circuits generate brief fault flags (<100 ns), insufficient to activate latching relays or PLC inputs. IC Role / Device Role / Timing Role: SN74AHC123AD extends fault pulses to 10–100 ms using adjustable R/C, enabling mechanical relay actuation or PLC scan cycle capture. Use Value: Provides fail-safe timing margin: pulse extension remains stable within ±1% across temperature due to matched internal timing references. |
Use Scenario: Oscilloscope or logic analyzer trigger outputs must align precisely with DUT stimulus edges across multiple test points. IC Role / Device Role / Timing Role: SN74AHC123AD generates synchronized, retriggerable delay pulses from master clock edges to coordinate multi-channel stimulus timing. Use Value: Achieves sub-15 ns inter-channel skew between Q outputs - critical for phase-aligned test vector generation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar monostable timing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74AHCT123AD | CMOS input thresholds (TTL-compatible), 4.5–5.5 V only - higher noise immunity at 5 V but incompatible below 4.5 V. | Best for legacy 5 V-only systems with TTL-level drivers; not suitable for mixed-voltage or 3.3 V domains. | Select when interfacing exclusively with 5 V TTL sources and requiring guaranteed VIH/VIL compatibility. |
| 74LVC123AD | Lower VCC range (1.65–5.5 V), 32 mA drive, faster propagation (≤ 7.5 ns at 3.3 V) - higher speed and broader voltage support. | Preferred for high-density, low-voltage portable designs where timing precision and power efficiency are critical. | Choose when operating below 2 V or requiring <8 ns delays; verify layout for enhanced ESD robustness (±3 kV HBM). |
Compared with SN74AHC123AD, SN74AHCT123AD offers tighter 5 V noise margins but sacrifices 2–4.5 V operation, while 74LVC123AD extends voltage range and speed at the cost of slightly higher quiescent current (60 μA vs. 40 μA) and different timing coefficient K.
Availability
SN74AHC123AD is available at Aetrix Electronics and suitable for industrial control panels, test instrumentation, motor drive safety monitoring, and embedded system timing functions requiring stable component supply across extended temperature ranges.
Supply support for SN74AHC123AD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with over 50 years of innovation in high-reliability timing and interface ICs.
The SN74AHC123AD belongs to TI's advanced AHC logic family, designed specifically for low-power, wide-supply-range monostable timing applications in industrial, automotive, and communications equipment where retriggerability and deterministic power-up behavior are essential.
FAQ
What is the minimum external timing capacitor value supported by SN74AHC123AD?
The SN74AHC123AD supports external timing capacitors down to 28 pF when used with Rext = 2 kΩ, yielding nominal pulse widths of 167–240 ns at 5 V. For values below 1000 pF, the multiplier factor K must be derived from Figure 7-8 in the datasheet, as K deviates from unity. Capacitors smaller than 28 pF are not characterized and may cause timing inaccuracies or failure to trigger reliably.
Can SN74AHC123AD operate reliably at 2.5 V supply voltage?
Yes, SN74AHC123AD is fully specified for operation from 2 V to 5.5 V, including 2.5 V. At 2.5 V, it maintains Schmitt-trigger input hysteresis (~0.35 V), supports 50 μA quiescent current, and delivers tPLH/tPHL ≤ 24 ns (CL = 50 pF). Output drive drops to ±4 mA, which remains sufficient for driving CMOS loads or small-signal transistors in low-voltage systems.
How does the retriggering mechanism work in SN74AHC123AD?
SN74AHC123AD allows retriggering during an active output pulse: a new valid edge on A or B input (per configured mode) restarts the timing cycle from zero, extending total pulse width. Minimum retrigger interval tMIR ≈ 0.3 × tw ensures reliable recognition. This behavior eliminates need for cascaded monostables or external logic to achieve long, variable-duration pulses.
Is SN74AHC123AD pin-compatible with older SN74LS123?
No, SN74AHC123AD is not pin-compatible with SN74LS123. While both are dual monostables, SN74LS123 uses 16-pin PDIP with different pin assignments (e.g., separate R/C pins per channel but no dedicated CLR per channel), lacks Schmitt inputs, and operates only at 5 V. SN74AHC123AD uses SOIC-16 with distinct pinout (e.g., shared VCC/GND, dual CLR inputs), requiring PCB redesign for replacement.
What is the maximum recommended external timing resistor value for SN74AHC123AD?
The datasheet specifies Rext up to 10 kΩ for stable operation with Cext ≥ 0.01 μF, yielding pulse widths up to 110 μs (CL = 50 pF). Higher values increase sensitivity to leakage and noise; TI does not characterize Rext beyond 10 kΩ. For pulses >1 ms, use Cext = 0.1 μF with Rext = 10 kΩ - verified to deliver 0.9–1.1 ms with ±1% variation between channels in same SN74AHC123AD package.
SN74AHC123AD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AHC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Logic Type:
- Monostable
- Independent Circuits:
- 2
- Schmitt Trigger Input:
- Yes
- Propagation Delay:
- 7.5 ns
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 2 V ~ 5.5 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SN74AHC123AD FAQ
1.How can I place an order for SN74AHC123AD through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74AHC123AD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74AHC123AD reliable?
The price and inventory of SN74AHC123AD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74AHC123AD is usually 5 days.
3.What payment methods are accepted for SN74AHC123AD?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74AHC123AD transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74AHC123AD?
SN74AHC123AD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74AHC123AD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74AHC123AD?
For technical support, including SN74AHC123AD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74AHC123AD requirements.
6.How does Aetrix verify that SN74AHC123AD is sourced from the original manufacturer or authorized distributors?
All SN74AHC123AD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74AHC123AD meets industry standards.
7.What is the process for return or replacement of SN74AHC123AD?
All SN74AHC123AD units undergo pre-shipment inspection (PSI). If there is an issue with SN74AHC123AD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74AHC123AD part is unused and in its original packaging.
Return procedure for SN74AHC123AD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74AHC123AD Tags

-
SN74LVC1G123DCUR
Texas Instruments
-
CD4047BM96
Texas Instruments

-
SN74LVC1G123DCTR
Texas Instruments
-
CD74HC221M96
Texas Instruments

-
CD14538BE
Texas Instruments

-
SN74LVC1G123YZPR
Texas Instruments

-
SN74LVC1G123DCUT
Texas Instruments
-
MC14538BDR2G
onsemi

-
74VHC123AMX
onsemi

-
LTC6993CS6-2#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-3#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-1#TRMPBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
