Texas Instruments SN74AHC367PWR
- Part No.:
- SN74AHC367PWR
- Manufacturer:
- Texas Instruments
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74AHC367PWR.pdf
- Description:
- IC BUF NON-INVERT 5.5V 16TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,733
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74AHC367 from Texas Instruments is a hex noninverting buffer/line driver with dual 3-state enable control (1OE, 2OE), designed for 2V–5.5V operation and used in bus interface, memory address driving, and signal routing applications. It features six independent channels grouped as two functional blocks (four-channel + two-channel), ±8 mA output drive at 5 V, 16-pin TSSOP package, and guaranteed operation from –40°C to +85°C.
For engineers reviewing the SN74AHC367 datasheet, SN74AHC367 pinout, SN74AHC367 application, or SN74AHC367 equivalent, key selection considerations include 3-state output timing (tPZH/tPLZ ≤ 12.5 ns at 3.3 V), input transition rate tolerance (100 ns/V), high-impedance state control logic, and compatibility with mixed-voltage system interfacing.
Technical Context
The SN74AHC367 implements dual independent 3-state buffer groups: one with four drivers (1A1–1A4 → 1Y1–1Y4) and another with two drivers (2A1–2A2 → 2Y1–2Y2), each controlled by its own active-low enable (1OE, 2OE). Outputs enter high-impedance when respective OE is high, enabling bidirectional bus sharing without external isolation.
It uses advanced CMOS AHC logic with rail-to-rail output swing, low dynamic power (Cpd = 22.4 pF), and robust ESD protection (±2000 V HBM). Input thresholds scale with VCC (VIH = 0.7×VCC min, VIL = 0.3×VCC max), supporting reliable interfacing across 2V–5.5V supply domains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2 V to 5.5 V - supports direct interface with 2.5 V, 3.3 V, and 5 V logic families without level shifters |
| Output Drive | ±8 mA at 5 V - sufficient to drive standard TTL loads or multiple CMOS inputs (fan-out ≥ 20) |
| Propagation Delay | 3.4 ns (tPLH/tPHL, CL = 15 pF, VCC = 5 V) - enables use in high-speed address/data buffering up to ~100 MHz |
| 3-State Enable Time | tPZH/tPLZ ≤ 8.5 ns (CL = 15 pF, VCC = 5 V) - ensures fast bus arbitration and minimal contention window |
| Input Thresholds | VIH = 3.85 V, VIL = 1.65 V at VCC = 5.5 V - provides >1.1 V noise margin for 5 V systems |
| Power Dissipation | Cpd = 22.4 pF - predicts typical dynamic power of ~0.37 mW/MHz at 3.3 V, suitable for low-power embedded control |
| Operating Temp | –40°C to +85°C - qualified for industrial temperature range without derating |
Pinout & Package
TSSOP-16 (PW) package: 5.00 mm × 6.4 mm body, 1.2 mm max height, lead pitch 0.65 mm, RoHS-compliant NIPDAU/SN finish, MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1OE, 2OE | Active-low 3-state enable inputs - tie high via pullup to ensure Hi-Z during power-up |
| 2, 4, 6, 10, 12, 14 | 1A1–1A4, 2A1–2A2 | Buffer input terminals - must be terminated to VCC or GND if unused to prevent floating |
| 3, 5, 7, 9, 11, 13 | 1Y1–1Y4, 2Y1–2Y2 | Noninverting 3-state outputs - present high-impedance state when corresponding OE is high |
| 8 | GND | Ground reference - requires low-inductance connection to PCB ground plane |
| 16 | VCC | Supply pin - bypass with 0.1 µF ceramic capacitor placed <1 cm from pin |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent 3-state control | Enables selective activation of two buffer groups (4-line + 2-line) on shared bus without contention |
| VCC-scalable input thresholds | VIH/VIL track VCC (0.7×/0.3×), ensuring noise-immune switching across 2V–5.5V supply range |
| Low dynamic power consumption | 22.4 pF power dissipation capacitance minimizes switching current in high-frequency clock/data paths |
| High ESD immunity | ±2000 V HBM rating allows safe handling in standard assembly environments without special precautions |
| Industrial temperature range | –40°C to +85°C operation verified per JEDEC JESD22-A104, suitable for factory automation and motor control |
Applications
| Memory Address Buffering | Industrial Bus Interface |
|---|---|
Use Scenario: Driving 16-bit address lines from a microcontroller to SRAM or flash memory in an industrial PLC. IC Role / Device Role / Timing Role: Noninverting buffer with 3-state outputs isolates address bus during memory read/write cycles and enables multi-master arbitration. Use Value: 8 mA drive strength ensures full logic swing across 15 cm PCB traces; tPLH < 7 ns maintains setup/hold timing margins at 25 MHz bus clock. | Use Scenario: Interfacing a 3.3 V FPGA I/O bank to legacy 5 V peripheral modules (e.g., ADCs, DACs) on a test equipment backplane. IC Role / Device Role / Timing Role: Voltage-tolerant level translator using VCC = 5 V and 3.3 V-compatible inputs to bridge logic domains. Use Value: VIH = 2.1 V at VCC = 3 V guarantees recognition of FPGA's 3.3 V HIGH; no external bias required. |
| Motor Controller Reset Logic | LED Indicator Driver |
Use Scenario: Combining four independent fault signals (over-temperature, over-current, undervoltage, watchdog timeout) into a single active-low RESET line for a BLDC motor driver IC. IC Role / Device Role / Timing Role: Active-low enabled buffer group (1OE) passes AND-logic-equivalent function when all inputs are HIGH. Use Value: Guaranteed VOL ≤ 0.44 V at 4 mA ensures valid LOW to motor controller's reset pin; tPHL < 6 ns prevents glitch-induced spurious resets. | Use Scenario: Driving eight discrete status LEDs from a 2.5 V microcontroller GPIO port while maintaining brightness consistency across varying supply conditions. IC Role / Device Role / Timing Role: Current-sourcing buffer (outputs pulled up externally) with 3-state disable for LED blanking during sleep mode. Use Value: IOH = –4 mA at 3.3 V delivers 5 mA sink current (with 330 Ω anode resistor); Hi-Z state eliminates leakage current in standby. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex buffer with 3-state output applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74AHCT367PWR | TTL-compatible inputs (VIH = 2 V min at VCC = 4.5–5.5 V); otherwise identical pinout, timing, and drive | Better suited for interfacing with legacy 5 V TTL logic where AHC's CMOS thresholds may cause marginal switching | Select SN74AHCT367PWR when connecting to 74LS/74F series devices; retain SN74AHC367PWR for pure CMOS or mixed-voltage systems |
| 74LVC367PW,118 | Lower VCC range (1.65–3.6 V); 24 mA drive at 3.3 V; different pinout (no 1A3/1Y3 on pins 6/7) | Optimized for 3.3 V-only portable electronics; not compatible with 5 V systems or SN74AHC367 footprint | Choose 74LVC367PW,118 only for battery-powered 3.3 V designs requiring higher drive; avoid for industrial 5 V or mixed-supply use |
Compared with SN74AHCT367PWR and 74LVC367PW,118, the SN74AHC367PWR uniquely balances wide supply range (2–5.5 V), CMOS input compatibility, and industrial temperature support - making it the preferred choice for programmable logic interface and bus isolation in factory automation hardware.
Availability
SN74AHC367PWR is available at Aetrix Electronics and suitable for industrial motor control, factory automation I/O modules, and embedded test equipment requiring stable component supply and long-term manufacturability.
Supply support for SN74AHC367PWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of experience in industrial-grade interface ICs.
The SN74AHC367 belongs to TI's AHC logic family - engineered for high-speed, low-power, 3-state bus interface in industrial and automotive control systems where reliability across voltage and temperature extremes is critical.
FAQ
What is the maximum recommended operating frequency for SN74AHC367PWR in a 50 pF load configuration?
The SN74AHC367PWR supports reliable operation up to approximately 80 MHz under typical conditions (VCC = 5 V, CL = 50 pF), based on worst-case propagation delay (tPLH/tPHL ≤ 9 ns) and minimum pulse width (tw ≥ 10 ns). For sustained 100 MHz operation, reduce load capacitance to ≤25 pF and verify timing margins with board-level simulation.
Can SN74AHC367PWR be used with a 2.5 V supply while interfacing to 3.3 V microcontroller GPIOs?
Yes - the SN74AHC367PWR operates down to 2 V and accepts input voltages up to VCC + 0.5 V. At VCC = 2.5 V, VIH = 1.75 V (0.7×VCC), which exceeds typical 3.3 V MCU output LOW threshold (0.8 V) and ensures robust HIGH detection. No level shifter is needed.
How should unused inputs be handled on SN74AHC367PWR to prevent malfunction?
All unused inputs on SN74AHC367PWR must be tied to a defined logic level - either VCC or GND - using direct connections or pullup/pulldown resistors. Floating inputs can cause increased ICC, erratic output states, or localized heating. For example, tie unused 1A3 (pin 6) to GND to force 1Y3 (pin 7) LOW when 1OE is active.
Does SN74AHC367PWR support hot insertion or live insertion into a powered backplane?
No - SN74AHC367PWR is not hot-swap rated. Its absolute maximum ratings specify VI and VO limits relative to GND and VCC. Inserting into a live backplane risks violating these limits (e.g., VCC ramping after inputs), potentially causing latch-up or permanent damage. Power sequencing must ensure VCC is stable before applying input signals.
What is the thermal resistance (RθJA) of SN74AHC367PWR in its TSSOP-16 package?
The SN74AHC367PWR in PW (TSSOP-16) package has a junction-to-ambient thermal resistance (RθJA) of 135.9°C/W under standard JEDEC test conditions (1-layer 2 oz copper, 1 in² pad). With proper PCB layout - including thermal vias under the exposed pad (if present) and 2+ oz internal ground planes - actual RθJA can improve to ≤65°C/W.
SN74AHC367PWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AHC
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
SN74AHC367PWR FAQ
1.How can I place an order for SN74AHC367PWR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74AHC367PWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74AHC367PWR reliable?
The price and inventory of SN74AHC367PWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74AHC367PWR is usually 5 days.
3.What payment methods are accepted for SN74AHC367PWR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74AHC367PWR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74AHC367PWR?
SN74AHC367PWR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74AHC367PWR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74AHC367PWR?
For technical support, including SN74AHC367PWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74AHC367PWR requirements.
6.How does Aetrix verify that SN74AHC367PWR is sourced from the original manufacturer or authorized distributors?
All SN74AHC367PWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74AHC367PWR meets industry standards.
7.What is the process for return or replacement of SN74AHC367PWR?
All SN74AHC367PWR units undergo pre-shipment inspection (PSI). If there is an issue with SN74AHC367PWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74AHC367PWR part is unused and in its original packaging.
Return procedure for SN74AHC367PWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74AHC367PWR Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
