Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Signal Switches, Multiplexers, Decoders

Texas Instruments SN74AHCT158D

Name: SN74AHCT158D
Brand: Texas Instruments
SKU: SN74AHCT158D
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SN74AHCT158D

Manufacturer:: Texas Instruments

Category:: Signal Switches, Multiplexers, Decoders

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: SN74AHCT158D.pdf

Description:: IC MULTIPLEXER 4 X 2:1 16SOIC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,371

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SN74AHCT158D from Texas Instruments is a quadruple 2-line to 1-line data selector/multiplexer IC designed for 4.5 V to 5.5 V V_CC operation, featuring TTL-voltage-compatible inputs, a common strobe (G) input, inverted outputs, and ±8 mA output drive capability. It routes one of two 4-bit data sources to four outputs based on the A/B select line, with propagation delays as low as 4.1 ns at 15 pF load - ideal for address/data routing in digital logic subsystems.

For engineers reviewing the SN74AHCT158D datasheet, SN74AHCT158D pinout, SN74AHCT158D application, or SN74AHCT158D equivalent, this device serves as a high-speed, low-power multiplexing solution compatible with TTL-level control signals in industrial control panels, legacy microprocessor bus interfaces, and programmable logic glue logic.

Technical Context

The SN74AHCT158D implements four independent 2:1 multiplexers sharing a single active-low strobe (G) and a common select input (A/B), enabling simultaneous selection of either the "A" or "B" input set across all four channels. Each channel provides true (non-inverted) data selection logic but delivers inverted outputs (Y = NOT[(A/B) ? A : B] AND NOT G).

Its architecture supports TTL-level input thresholds (V_IL = 0.8 V, V_VIH = 2.0 V) while operating from a 5-V supply, and guarantees latch-up immunity exceeding 250 mA per JESD 17. Propagation delay variation is tightly controlled - t_PLH/t_PHL from A/B to Y is 5.3–9.5 ns (15 pF), and from G to Y is 5.6–10 ns (15 pF), ensuring deterministic timing in synchronous bus arbitration.

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	4.5 V to 5.5 V - ensures compatibility with standard 5-V TTL and CMOS systems without level-shifting.
Output Drive	±8 mA - sufficient to directly drive multiple 74-series TTL inputs or small capacitive loads (<15 pF) without buffering.
t_PLH/t_PHL (A/B → Y)	5.3 ns (min) to 9.5 ns (max) at 15 pF - enables reliable operation in 100-MHz clock-domain edge sampling.
Input Compatibility	TTL-voltage - accepts 0.8 V / 2.0 V logic thresholds, eliminating need for external level translators when interfacing with legacy 74LS/74F devices.
Strobe Function	Active-low G input forces all outputs high when asserted - provides hardware-based channel disable and bus isolation.
ESD Rating	2000-V HBM - meets industrial IEC 61000-4-2 system-level robustness requirements without added protection circuitry.
Operating Temp	–40°C to +85°C - qualified for extended-temperature industrial environments including factory automation controllers.

Pinout & Package

SN74AHCT158D is housed in a 16-pin SOIC (D) package (5.3 mm × 10.2 mm, 1.75 mm height), JEDEC MS-012 compliant, with 1.27 mm pitch and NIPDAU lead finish. RoHS-compliant and MSL Level-1 rated.

Pin/Terminal	Circuit Role	Design Meaning
1 (1A)	Channel 1 Data Input A	First bit of source-A data word; routed to 1Y when A/B = L and G = L.
2 (1B)	Channel 1 Data Input B	First bit of source-B data word; routed to 1Y when A/B = H and G = L.
3 (2A)	Channel 2 Data Input A	Second bit of source-A data word; synchronized with 1A, 3A, 4A under same A/B/G control.
4 (2B)	Channel 2 Data Input B	Second bit of source-B data word; shares A/B select and strobe with other channels.
5 (3A)	Channel 3 Data Input A	Third bit of source-A data word; enables full 4-bit parallel multiplexing without inter-channel skew.
6 (3B)	Channel 3 Data Input B	Third bit of source-B data word; maintains identical timing behavior across all four channels.
7 (4A)	Channel 4 Data Input A	Fourth bit of source-A data word; completes quad 2:1 function for byte-wide data path selection.
8 (4B)	Channel 4 Data Input B	Fourth bit of source-B data word; allows full 4-bit bus switching with single A/B control line.
9 (G)	Common Strobe Input	Active-low enable: drives all outputs high when HIGH; enables multiplexing only when LOW.
10 (A/B)	Common Select Input	Determines source: LOW selects all A inputs (1A–4A); HIGH selects all B inputs (1B–4B).
11 (1Y)	Channel 1 Inverted Output	Complemented output of selected 1A or 1B; logic high when unselected or strobed, low when selected and driven.
12 (2Y)	Channel 2 Inverted Output	Complemented output of selected 2A or 2B; matches 1Y timing within 0.3 ns typical skew.
13 (3Y)	Channel 3 Inverted Output	Complemented output of selected 3A or 3B; guaranteed monotonic transition under all valid input combinations.
14 (4Y)	Channel 4 Inverted Output	Complemented output of selected 4A or 4B; supports wired-OR expansion via external pull-ups if needed.
15 (GND)	Ground Reference	Primary return path for all internal logic and output drivers; requires low-inductance PCB connection.
16 (V_CC)	Supply Voltage	5-V nominal power rail; decoupling capacitor (0.1 µF ceramic) required within 5 mm of pin for noise immunity.

Key Features

Feature	Design Value
TTL-Compatible Inputs	Accepts standard 74LS/74F logic thresholds (0.8 V / 2.0 V), enabling direct interface with legacy TTL without level shifters.
Common Strobe Control	Single active-low G input disables all four outputs simultaneously - simplifies bus arbitration and reduces control line count.
Inverted Outputs	Delivers complementary logic levels (Y = NOT selected input), supporting active-low enable schemes and reducing external inverters.
Latch-Up Immunity	Exceeds 250 mA per JESD 17 - prevents destructive latch-up during hot-swap or ESD transients in industrial backplanes.
Low Propagation Skew	Matched t_PLH/t_PHL across channels (<0.5 ns typical) ensures clean 4-bit word alignment in time-critical data paths.

Applications

Industrial PLC I/O Expansion	Legacy Microprocessor Address Decoding
Use Scenario: Routing sensor data from dual analog front-end channels to a single ADC input in modular PLC racks. IC Role / Device Role / Timing Role: Quad 2:1 selector switches between redundant signal paths under firmware-controlled A/B and G lines. Use Value: Eliminates need for four discrete 74HC157s, reducing board area by 35% and interconnect skew by 1.2 ns.	Use Scenario: Selecting between two memory-mapped peripheral address spaces (e.g., UART vs SPI controller) on an 8051-based design. IC Role / Device Role / Timing Role: Generates chip-select signals for two banks using shared address bits and strobe synchronization. Use Value: Enables zero-wait-state decoding with 9.5 ns max delay - meets 8051's 12-MHz bus timing budget.
Test Equipment Signal Routing	Digital Audio Multiplexer Interface
Use Scenario: Switching calibration reference signals into DMM input stages during self-test sequences. IC Role / Device Role / Timing Role: Provides glitch-free, strobe-gated selection of precision voltage references under microcontroller control. Use Value: Active-low G ensures outputs float high during test setup - preventing unintended loading of reference sources.	Use Scenario: Selecting between left/right channel audio data streams in a TDM-based codec interface. IC Role / Device Role / Timing Role: Routes 4-bit control words (e.g., gain, mute, filter config) from dual DSP cores to shared configuration registers. Use Value: Inverted outputs match active-low register write-enable polarity, removing external inverters and saving 4 BOM line items.

Industrial PLC I/O Expansion

Legacy Microprocessor Address Decoding

Use Scenario: Routing sensor data from dual analog front-end channels to a single ADC input in modular PLC racks.

IC Role / Device Role / Timing Role: Quad 2:1 selector switches between redundant signal paths under firmware-controlled A/B and G lines.

Use Value: Eliminates need for four discrete 74HC157s, reducing board area by 35% and interconnect skew by 1.2 ns.

Use Scenario: Selecting between two memory-mapped peripheral address spaces (e.g., UART vs SPI controller) on an 8051-based design.

IC Role / Device Role / Timing Role: Generates chip-select signals for two banks using shared address bits and strobe synchronization.

Use Value: Enables zero-wait-state decoding with 9.5 ns max delay - meets 8051's 12-MHz bus timing budget.

Test Equipment Signal Routing

Digital Audio Multiplexer Interface

Use Scenario: Switching calibration reference signals into DMM input stages during self-test sequences.

IC Role / Device Role / Timing Role: Provides glitch-free, strobe-gated selection of precision voltage references under microcontroller control.

Use Value: Active-low G ensures outputs float high during test setup - preventing unintended loading of reference sources.

Use Scenario: Selecting between left/right channel audio data streams in a TDM-based codec interface.

IC Role / Device Role / Timing Role: Routes 4-bit control words (e.g., gain, mute, filter config) from dual DSP cores to shared configuration registers.

Use Value: Inverted outputs match active-low register write-enable polarity, removing external inverters and saving 4 BOM line items.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2:1 multiplexer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74AHCT157D	Non-inverting outputs; identical pinout and timing; same V_CC, drive, and temp range.	Requires external inversion for active-low enable schemes; unsuitable where inverted output logic is mandatory.	Select SN74AHCT157D only when system logic expects true (non-inverted) outputs and timing-critical paths allow extra gate delay.
74LVC157D	3.3-V only (1.65–3.6 V); lower drive (±24 mA); faster t_PHL (2.5 ns typ); different input thresholds (V_IL = 0.7×V_CC).	Not interoperable with 5-V TTL buses; requires level translation; incompatible with legacy 5-V control signals.	Choose 74LVC157D only in new 3.3-V designs prioritizing speed and lower power; avoid in mixed-voltage or retrofit applications.

Compared with SN74AHCT158D, SN74AHCT157D offers functional equivalence except output polarity, while 74LVC157D trades 5-V compatibility for higher speed and lower voltage operation - making SN74AHCT158D the sole drop-in replacement for existing 5-V TTL-interfaced multiplexer designs requiring inverted outputs.

Availability

SN74AHCT158D is available at Aetrix Electronics and suitable for industrial PLC I/O modules, legacy microprocessor bus interfaces, and automated test equipment requiring stable component supply, long-term obsolescence management, and traceable sourcing.

Supply support for SN74AHCT158D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic solutions with broad industrial, automotive, and communications portfolio coverage.

The SN74AHCT logic family targets 5-V mixed-signal systems needing TTL-compatible inputs, robust ESD/latch-up performance, and precise timing - specifically engineered for reliability in factory automation, instrumentation, and legacy upgrade applications.

FAQ

What is the function of the G (strobe) input on the SN74AHCT158D?

The G input on the SN74AHCT158D is an active-low strobe that globally enables or disables all four multiplexer outputs. When G is high, all Y outputs are forced high regardless of A/B or data inputs; when G is low, the selected A or B inputs pass through (inverted) to the corresponding Y outputs. This provides hardware-level bus isolation and simplifies timing-critical enable sequencing in multi-device systems - a key feature distinguishing SN74AHCT158D from non-strobed alternatives like SN74AHCT157D.

Does the SN74AHCT158D support 3.3-V input logic levels?

No, the SN74AHCT158D does not reliably accept 3.3-V logic levels as valid inputs. Its specified VIH is 2.0 V minimum and VIL is 0.8 V maximum at VCC = 4.5–5.5 V, optimized for TTL-compatible 5-V signaling. A 3.3-V high signal may fall below the guaranteed VIH threshold, risking metastability or incorrect selection. For 3.3-V systems, TI recommends the 74LVC157 series instead - but SN74AHCT158D remains optimal for 5-V legacy interfaces where SN74AHCT158D must maintain strict TTL voltage compatibility.

Can unused inputs on the SN74AHCT158D be left floating?

No, unused inputs on the SN74AHCT158D must not be left floating. Per TI application report SCBA004, all unused inputs - including A/B, G, and any unconnected 1A–4B pins - must be tied to VCC or GND to prevent increased ICC, oscillation, or ESD susceptibility. Floating inputs cause undefined internal node voltages, leading to excessive current draw (up to 20 µA typical increase) and potential logic errors. This requirement applies universally across all SN74AHCT158D operating conditions and is critical to ensure SN74AHCT158D reliability in industrial deployments.

What is the maximum capacitive load the SN74AHCT158D can drive while maintaining specified timing?

The SN74AHCT158D is characterized for CL = 15 pF and CL = 50 pF loads in its datasheet, with propagation delays specified up to 12 ns (max) at 50 pF. While it can physically drive >50 pF, timing margins degrade beyond that point - t_PHL increases by ~0.15 ns per additional pF above 50 pF. For designs requiring guaranteed 9.5 ns max delay (e.g., 100-MHz bus timing), keep total load ≤50 pF, including trace capacitance, probe effects, and input capacitance of downstream devices. This constraint is essential for maintaining SN74AHCT158D timing compliance in high-speed digital systems.

Is the SN74AHCT158D pin-compatible with the SN74LS158?

Yes, the SN74AHCT158D is pin-compatible with the SN74LS158 in the same SOIC (D) package, sharing identical pin assignments, pin count (16), and footprint. However, SN74AHCT158D offers superior specs: wider VCC range (4.5–5.5 V vs 4.75–5.25 V), higher output drive (±8 mA vs ±0.4 mA), faster propagation (4.1 ns min vs 12 ns min), and enhanced ESD/latch-up protection. As a drop-in replacement, SN74AHCT158D upgrades legacy LS-based designs without PCB changes - preserving layout while improving noise immunity and timing margin.

SN74AHCT158D Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74AHCT

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Bulk

Product Status:: Active

Type:: Multiplexer

Circuit:: 4 x 2:1

Independent Circuits:: 1

Current - Output High, Low:: 8mA, 8mA

Voltage Supply Source:: Single Supply

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

SN74AHCT158D FAQ

1.How can I place an order for SN74AHCT158D through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74AHCT158D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74AHCT158D reliable?

The price and inventory of SN74AHCT158D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74AHCT158D is usually 5 days.

3.What payment methods are accepted for SN74AHCT158D?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74AHCT158D transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74AHCT158D?

SN74AHCT158D orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74AHCT158D order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74AHCT158D?

For technical support, including SN74AHCT158D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74AHCT158D requirements.

6.How does Aetrix verify that SN74AHCT158D is sourced from the original manufacturer or authorized distributors?

All SN74AHCT158D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74AHCT158D meets industry standards.

7.What is the process for return or replacement of SN74AHCT158D?

All SN74AHCT158D units undergo pre-shipment inspection (PSI). If there is an issue with SN74AHCT158D, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74AHCT158D part is unused and in its original packaging.

Return procedure for SN74AHCT158D:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…