Texas Instruments SN74AHCT367D
- Part No.:
- SN74AHCT367D
- Manufacturer:
- Texas Instruments
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74AHCT367D.pdf
- Description:
- IC BUF NON-INVERT 5.5V 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,057
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Product details
Overview
SN74AHCT367D from Texas Instruments is a hex noninverting buffer/line driver with dual 3-state output enables (1OE, 2OE), TTL-compatible inputs, true outputs, and 5-V operation. It delivers 8.5 ns max propagation delay at 5 V/15 pF, ±25 mA output drive per channel, and operates across –40°C to 125°C for memory address buffering and bus interface applications in telecom infrastructure and network switches.
For engineers reviewing the SN74AHCT367D datasheet, SN74AHCT367D pinout, SN74AHCT367D application, or SN74AHCT367D equivalent, this page provides verified functional modes, switching characteristics, thermal metrics for SOIC-16, ESD robustness (2000 V HBM/CDM), and real-world layout guidance for minimizing ringing in 3-state bus systems.
Technical Context
The SN74AHCT367D implements two independent 3-state buffer groups: one 4-channel (1A1–1A4 → 1Y1–1Y4) and one 2-channel (2A1–2A2 → 2Y1–2Y2), each controlled by its own active-low enable (1OE, 2OE). All outputs are noninverting and support high-impedance states when enables are high.
It uses advanced CMOS technology optimized for 5-V supply, accepts TTL-level inputs (VIH = 2 V, VIL = 0.8 V), supports 3.3-V-to-5-V voltage translation, and features slow edge rates to suppress output ringing on light-loaded buses - critical for stable signal integrity in clock distribution and address multiplexing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 4.5 V to 5.5 V - ensures compatibility with standard 5-V logic rails and tolerance against supply ripple. |
| Propagation Delay (tPLH/tPHL) | 8.5 ns max at –40°C to 125°C, CL = 15 pF - defines worst-case timing margin for synchronous bus interfaces. |
| Output Drive (IOL/IOH) | ±8 mA at VCC = 4.5 V - sufficient for driving multiple TTL loads or short PCB traces without external buffering. |
| Input Voltage Thresholds | VIH = 2 V min, VIL = 0.8 V max - guarantees reliable recognition of 3.3-V logic levels in mixed-voltage systems. |
| ESD Protection | ±2000 V HBM and CDM - meets JEDEC JESD22-A114 and JESD22-C101, enabling robust handling in automated assembly. |
| Operating Temperature | –40°C to 125°C - supports industrial and automotive under-hood environments without derating. |
| Quiescent Current (ICC) | 40 µA max at 125°C - enables low-static-power operation in always-on control logic stages. |
Pinout & Package
SN74AHCT367D is supplied in a 16-pin SOIC (D) package measuring 9.9 mm × 6.0 mm (body: 9.9 mm × 3.90 mm), with standard 1.27-mm pitch and gull-wing leads suitable for reflow soldering.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1OE, 2OE | Active-low output enables - independently disable Group 1 (pins 2–9) or Group 2 (pins 11–14) to prevent bus contention. |
| 2, 4, 6, 10 | 1A1–1A4 | Group 1 input channels - accept TTL/CMOS signals for noninverting buffering to Y1–Y4. |
| 3, 5, 7, 9 | 1Y1–1Y4 | Group 1 true outputs - present high-impedance state when 1OE = high; otherwise replicate A1–A4. |
| 11, 14 | 2A1, 2A2 | Group 2 input channels - drive corresponding Y outputs only when 2OE = low. |
| 12, 13 | 2Y1, 2Y2 | Group 2 true outputs - isolated from Group 1 for independent bus segment control. |
| 8 | GND | Ground reference - must be low-impedance connection to minimize ground bounce during switching. |
| 16 | VCC | 5-V power supply - requires local 0.1-µF bypass capacitor adjacent to pin for noise suppression. |
Key Features
| Feature | Design Value |
|---|---|
| TTL-compatible inputs | Accepts 3.3-V logic high (2 V min) directly - eliminates level-shifter need in mixed-voltage designs. |
| Slow edge rate control | Minimizes overshoot/undershoot on unterminated traces - reduces EMI and improves signal integrity in dense layouts. |
| High-impedance output state | Enables multi-driver bus architectures without external pull-ups or arbitration logic. |
| Latch-up immunity | Exceeds 100 mA per JESD78 Class II - prevents destructive latch-up during transient overvoltage events. |
| Industrial temperature range | –40°C to 125°C operation - validated for use in base station RF modules and industrial PLC backplanes. |
Applications
| Telecom Infrastructure | Network Switches |
|---|---|
Use Scenario: Address/data bus isolation between FPGA and DDR2 memory controller in 4G/LTE baseband units. IC Role / Device Role / Timing Role: 3-state buffer managing bidirectional address lines with precise enable timing to avoid bus contention during read/write transitions. Use Value: 8.5 ns max propagation delay ensures setup/hold compliance at 100-MHz bus clocks; ±25 mA drive sustains signal integrity over 10-cm FR4 traces. |
Use Scenario: Control signal fanout from management MCU to multiple PHY reset and LED indicator lines in Layer 3 Ethernet switches. IC Role / Device Role / Timing Role: Noninverting line driver replicating GPIO outputs while isolating MCU from load capacitance and ESD transients. Use Value: 2000 V HBM/CDM protection eliminates external TVS diodes; 0.44 V VOL at 8 mA guarantees clean low-level signaling to 3.3-V PHYs. |
| TVs | Electronic Points of Sale |
Use Scenario: HDMI CEC and IR receiver signal conditioning in smart TV mainboards with mixed 3.3-V/5-V domains. IC Role / Device Role / Timing Role: Voltage translator buffering TTL-level IR pulses into 5-V system logic while maintaining sub-10 ns timing accuracy. Use Value: VIH = 2 V threshold allows direct connection to 3.3-V microcontrollers; slow edges suppress ringing on long flex-cable runs. |
Use Scenario: Keypad matrix scanning and display backlight control in ruggedized POS terminals deployed in retail environments. IC Role / Device Role / Timing Role: Hex buffer distributing scan row signals and enabling LED drivers with independent enable control per group. Use Value: Dual OE pins allow staggered activation to reduce peak current draw; 125°C rating supports sealed enclosures with passive cooling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex buffer with 3-state output applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74AHCT244D | Octal (8-channel) noninverting buffer with dual OE; identical VCC, timing, and drive specs but higher channel count. | Better suited for full 8-bit data bus buffering; requires more PCB area and routing resources than needed for 6-signal applications. | Select SN74AHCT244D only when expanding from 6 to 8 parallel signals - avoids redesign but increases cost and footprint. |
| 74LVC244APW | 3.3-V-only operation (1.65–3.6 V); lower propagation delay (4.4 ns typ), but incompatible with 5-V buses and lacks TTL input thresholds. | Applicable only in pure 3.3-V systems; cannot replace SN74AHCT367D in 5-V or mixed-voltage contexts without level shifters. | Choose 74LVC244APW for new 3.3-V designs prioritizing speed and low power; not a drop-in replacement for SN74AHCT367D. |
Compared with SN74AHCT367D, SN74AHCT244D offers higher channel density at identical voltage and timing specs, while 74LVC244APW trades 5-V compatibility and TTL input support for lower voltage operation and faster switching - making SN74AHCT367D uniquely suited for legacy 5-V bus interfacing with mixed-signal tolerance.
Availability
SN74AHCT367D is available at Aetrix Electronics and suitable for telecom infrastructure, network switches, and electronic points of sale requiring stable component supply, long-term industrial temperature support, and proven 3-state bus interface reliability.
Supply support for SN74AHCT367D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog and embedded processing solutions, with over 90 years of innovation in logic, power management, and signal chain technologies.
The SN74AHCT367D belongs to TI's AHCT logic family, engineered for 5-V systems requiring TTL compatibility, robust ESD performance, and precise 3-state control - specifically targeting memory addressing, clock distribution, and bus transceivers in industrial and communications equipment.
FAQ
What is the maximum operating temperature for the SN74AHCT367D?
The SN74AHCT367D is rated for continuous operation from –40°C to 125°C ambient temperature, validated per JEDEC JESD78 latch-up testing and thermal characterization. This makes SN74AHCT367D suitable for deployment in enclosed industrial enclosures and telecom base station hardware where passive cooling dominates.
Does the SN74AHCT367D support 3.3-V input logic levels?
Yes, the SN74AHCT367D accepts 3.3-V logic inputs reliably due to its TTL-compatible input thresholds: VIH = 2 V minimum and VIL = 0.8 V maximum. This allows direct connection to 3.3-V microcontrollers without level-shifting circuitry, a key design advantage confirmed in TI's Application Report SCBA004.
Can the SN74AHCT367D drive multiple TTL loads simultaneously?
Yes, the SN74AHCT367D can drive up to 10 standard TTL loads per output (based on IOL = 8 mA, VOL ≤ 0.44 V at VCC = 4.5 V), as specified in Section 5.5 of the datasheet. Its ±25 mA absolute maximum output current also permits short-duration surge handling during bus contention scenarios.
What is the purpose of the dual output-enable pins (1OE and 2OE) on the SN74AHCT367D?
The dual active-low enables (1OE for channels 1Y1–1Y4; 2OE for 2Y1–2Y2) allow independent control of two logical buffer groups. This enables selective bus segmentation - for example, holding memory address lines active while disabling peripheral control signals - preventing contention and simplifying timing in multi-master systems using SN74AHCT367D.
Is the SN74AHCT367D pin-compatible with other packages in the same family?
No - the SN74AHCT367D (SOIC-16) shares identical pinout and function with SN74AHCT367DBR (SSOP-16), SN74AHCT367DGVR (TVSOP-16), and SN74AHCT367PWR (TSSOP-16), as confirmed in TI's Package Information table and Pin Configuration Figure 4-1. All variants use the same 16-pin mapping and logic behavior.
SN74AHCT367D Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AHCT
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SN74AHCT367D FAQ
1.How can I place an order for SN74AHCT367D through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74AHCT367D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74AHCT367D reliable?
The price and inventory of SN74AHCT367D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74AHCT367D is usually 5 days.
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Once your SN74AHCT367D order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74AHCT367D?
For technical support, including SN74AHCT367D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74AHCT367D requirements.
6.How does Aetrix verify that SN74AHCT367D is sourced from the original manufacturer or authorized distributors?
All SN74AHCT367D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74AHCT367D meets industry standards.
7.What is the process for return or replacement of SN74AHCT367D?
All SN74AHCT367D units undergo pre-shipment inspection (PSI). If there is an issue with SN74AHCT367D, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74AHCT367D part is unused and in its original packaging.
Return procedure for SN74AHCT367D:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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