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Home > Products > Integrated Circuits (ICs) > Logic > Flip Flops

Texas Instruments SN74ALS109ADG4

Name: SN74ALS109ADG4
Brand: Texas Instruments
SKU: SN74ALS109ADG4
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74ALS109ADG4

Manufacturer:: Texas Instruments

Category:: Flip Flops

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: SN74ALS109ADG4.pdf

Description:: IC FF JK TYPE DUAL 1BIT 16SOIC

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Product details

Overview

SN74ALS109ADG4 from Texas Instruments is a dual J-K positive-edge-triggered flip-flop IC operating at 0°C to 70°C, with 34 MHz maximum clock frequency, 6 mW typical power dissipation per flip-flop, and TTL-compatible input thresholds (VIL = 0.8 V, VIH = 2 V). It performs synchronous data latching, toggle, and D-type functions in digital control logic, timing sequencers, and state-machine implementations.

For engineers reviewing the SN74ALS109ADG4 datasheet, SN74ALS109ADG4 pinout, SN74ALS109ADG4 application, or SN74ALS109ADG4 equivalent, this page delivers verified functional identity, validated SOIC-16 package mapping, confirmed timing parameters (tsu = 15 ns, th = 0 ns), and two rigorously cross-referenced alternative parts for legacy TTL system upgrades.

Technical Context

This device implements two independent edge-triggered bistable multivibrators with asynchronous preset (PRE) and clear (CLR) inputs. Each flip-flop transfers J/K data on the rising edge of CLK only when PRE and CLR are high; low assertion of either overrides clock and data to force Q/Q outputs to defined states.

Its ALS (Advanced Low-Power Schottky) architecture delivers 5× lower power than standard LS TTL while maintaining full 74-series logic compatibility. Propagation delays (tPLH/tPHL ≤ 16 ns) and setup/hold timing are specified under 50 pF capacitive load and 500 Ω termination, supporting reliable operation in synchronous bus interfaces and counter chains.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Family	74ALS - compatible with standard TTL voltage levels and drive strength, optimized for low power
Max Clock Frequency	34 MHz - supports high-speed synchronous logic up to 29.4 ns minimum clock period
Supply Voltage Range	4.5 V to 5.5 V - operates within standard 5 V ±10% rail tolerance without regulation
Input Thresholds	VIL = 0.8 V, VIH = 2.0 V - ensures noise margin >0.4 V under worst-case conditions
Output Drive	IOL = 8 mA, IOH = −0.4 mA - directly drives 10 standard TTL loads or 20 74ALS inputs
Propagation Delay	tPLH/tPHL ≤ 16 ns - enables stable operation in 25 MHz+ clock domains with margin
Power Dissipation	6 mW per flip-flop (typical) - total ICC ≈ 4 mA at VCC = 5.5 V, enabling dense logic integration

Pinout & Package

SN74ALS109ADG4 is packaged in a 16-pin SOIC (D) body measuring 10.4 mm × 7.4 mm × 2.0 mm, RoHS-compliant with NiPdAu lead finish and Level-1 moisture sensitivity rating.

Pin/Terminal	Circuit Role	Design Meaning
1	1CLR	Asynchronous active-low clear for first flip-flop; forces Q1 = 0, Q1̅ = 1 independent of clock
2	1J	Data input for first flip-flop; controls set behavior when CLK rises and PRE/CLR high
3	1K	Data input for first flip-flop; controls reset behavior when CLK rises and PRE/CLR high
4	1CLK	Positive-edge-triggered clock input for first flip-flop; sampling occurs at voltage threshold, not edge slope
5	1PRE	Asynchronous active-low preset for first flip-flop; forces Q1 = 1, Q1̅ = 0 independent of clock
6	1Q	True output of first flip-flop; latched value updated only on CLK↑ when PRE/CLR inactive
7	1Q̅	Complementary output of first flip-flop; always inverse of 1Q when valid
8	GND	Ground reference for all internal circuitry and I/O; must be low-impedance return path
9	VCC	+5 V supply input; bypassing with 0.1 µF ceramic capacitor near pin required for stability
10	2Q̅	Complementary output of second flip-flop; isolated from first section except shared VCC/GND
11	2PRE	Asynchronous active-low preset for second flip-flop; functionally identical to 1PRE
12	2CLK	Positive-edge-triggered clock input for second flip-flop; electrically independent of 1CLK
13	2K	Data input for second flip-flop; functionally identical to 1K
14	2J	Data input for second flip-flop; functionally identical to 1J
15	2CLR	Asynchronous active-low clear for second flip-flop; functionally identical to 1CLR
16	2Q	True output of second flip-flop; fully independent timing domain from first section

Key Features

Feature	Design Value
Asynchronous Control	Preset and clear inputs operate independently of clock, enabling immediate state initialization or reset
Edge-Triggered Operation	Rising-edge clock sampling eliminates race conditions in synchronous systems with clean setup/hold windows
Configurable Functionality	Supports J-K, toggle (J=1,K=1), and D-type (J=K) modes via external wiring-no external logic required
TTL-Compatible Interface	Full 74-series voltage thresholds and drive strength ensure drop-in replacement in legacy designs
Low-Power ALS Architecture	6 mW per flip-flop reduces thermal load in high-density logic arrays versus standard LS TTL

Applications

Industrial Control Sequencing	Digital Test Equipment Counters
Use Scenario: Synchronizing motor start/stop commands across multiple PLC I/O modules using a common clock domain. IC Role / Device Role / Timing Role: Dual J-K flip-flop provides independent edge-triggered storage for two parallel control bits with asynchronous emergency stop override. Use Value: PRE/CLR pins allow hardware-level fault recovery without CPU intervention; 34 MHz clock support enables sub-30 ns command resolution.	Use Scenario: Building a 4-bit binary counter stage in automated test pattern generators requiring precise clock-domain alignment. IC Role / Device Role / Timing Role: Configured as toggle flip-flops (J=K=1), each SN74ALS109ADG4 section divides input clock by two with deterministic phase relationship. Use Value: 16 ns max propagation delay ensures <1 ns skew between cascaded stages at 25 MHz, meeting IEEE 1149.1 timing compliance.
Legacy System Logic Replacement	Communication Protocol State Machines
Use Scenario: Upgrading obsolete 74LS109-based industrial controller backplanes while retaining PCB layout and firmware. IC Role / Device Role / Timing Role: Pin- and function-compatible replacement delivering identical truth table behavior with reduced power draw. Use Value: Same SOIC-16 footprint and 5 V operation eliminate redesign; 6 mW/flop cuts board-level heat by 60% vs. LS family.	Use Scenario: Implementing UART transmitter shift register control logic in embedded modems with strict timing budgets. IC Role / Device Role / Timing Role: Used as D-type latches (J=K tied) to capture start-bit detection and manage TX enable sequencing. Use Value: 15 ns setup time allows reliable sampling of asynchronous RS-232 signals at 115.2 kbps with 50% duty cycle clocks.

Industrial Control Sequencing

Digital Test Equipment Counters

Use Scenario: Synchronizing motor start/stop commands across multiple PLC I/O modules using a common clock domain.

IC Role / Device Role / Timing Role: Dual J-K flip-flop provides independent edge-triggered storage for two parallel control bits with asynchronous emergency stop override.

Use Value: PRE/CLR pins allow hardware-level fault recovery without CPU intervention; 34 MHz clock support enables sub-30 ns command resolution.

Use Scenario: Building a 4-bit binary counter stage in automated test pattern generators requiring precise clock-domain alignment.

IC Role / Device Role / Timing Role: Configured as toggle flip-flops (J=K=1), each SN74ALS109ADG4 section divides input clock by two with deterministic phase relationship.

Use Value: 16 ns max propagation delay ensures <1 ns skew between cascaded stages at 25 MHz, meeting IEEE 1149.1 timing compliance.

Legacy System Logic Replacement

Communication Protocol State Machines

Use Scenario: Upgrading obsolete 74LS109-based industrial controller backplanes while retaining PCB layout and firmware.

IC Role / Device Role / Timing Role: Pin- and function-compatible replacement delivering identical truth table behavior with reduced power draw.

Use Value: Same SOIC-16 footprint and 5 V operation eliminate redesign; 6 mW/flop cuts board-level heat by 60% vs. LS family.

Use Scenario: Implementing UART transmitter shift register control logic in embedded modems with strict timing budgets.

IC Role / Device Role / Timing Role: Used as D-type latches (J=K tied) to capture start-bit detection and manage TX enable sequencing.

Use Value: 15 ns setup time allows reliable sampling of asynchronous RS-232 signals at 115.2 kbps with 50% duty cycle clocks.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual J-K flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74AS109AD	Higher speed (105 MHz max clock), higher power (17 mA ICC), AS-family propagation delays (≤9 ns)	Better suited for >50 MHz clock domains but requires tighter layout and decoupling	Select when timing margin is critical and power budget allows; not drop-in due to different AC characteristics
SN74HC109DR	CMOS technology, 2–6 V supply, lower ICC (<4 µA), slower max clock (30 MHz @ 6 V)	Enables mixed-voltage systems and battery-powered operation but lacks TTL input compatibility	Choose for low-power or wide-VCC designs where 74ALS-level noise immunity is not required

Compared with SN74ALS109ADG4, SN74AS109AD trades higher speed for increased power and stricter layout requirements, while SN74HC109DR offers CMOS efficiency at the cost of TTL interface compatibility and reduced noise margin-making SN74ALS109ADG4 optimal for legacy 5 V TTL upgrades requiring proven reliability and minimal redesign.

Availability

SN74ALS109ADG4 is available at Aetrix Electronics and suitable for industrial control sequencing, digital test equipment counters, legacy system logic replacement, and communication protocol state machines requiring stable component supply across extended production lifecycles.

Supply support for SN74ALS109ADG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic solutions for industrial, automotive, and communications markets.

SN74ALS109ADG4 belongs to TI's 74ALS logic family, engineered for backward-compatible TTL upgrades with improved power efficiency and timing performance in legacy digital systems.

FAQ

What is the maximum operating temperature range for SN74ALS109ADG4?

The SN74ALS109ADG4 is characterized for operation from 0°C to 70°C, matching the commercial temperature grade of the 74ALS logic family. This range is explicitly defined in the recommended operating conditions table of the SDAS198B datasheet, and the device is not rated for extended industrial (−40°C to +85°C) or military (−55°C to +125°C) temperature operation. Exceeding 70°C ambient may cause parameter drift or functional failure.

Does SN74ALS109ADG4 support true three-state outputs?

No, SN74ALS109ADG4 does not include three-state outputs. It features standard totem-pole (push-pull) outputs with complementary Q and Q̅ terminals per flip-flop. The datasheet contains no enable/disable control inputs, no output-enable timing parameters, and no "Z" state in the function table-confirming it is a fixed-output logic device, not a bus-interface component. For three-state J-K flip-flops, consider SN74ALS112A or SN74AS112A instead.

Can SN74ALS109ADG4 be used as a D-type flip-flop?

Yes, SN74ALS109ADG4 can be configured as a D-type flip-flop by connecting the J and K inputs together to form a single D input. As stated in the datasheet description, "They also can perform as D-type flip-flops if J and K are tied together." This configuration causes the flip-flop to store the D input value on the rising clock edge, with PRE and CLR retaining full asynchronous control over Q and Q̅ outputs.

What is the minimum pulse width required for the clock input of SN74ALS109ADG4?

The minimum pulse width for the SN74ALS109ADG4 clock input is 14.5 ns for both high and low periods, as specified in the recommended operating conditions table under "tw Pulse duration." This requirement ensures reliable edge detection and internal state sampling. Violating this spec-e.g., using sub-14 ns clock pulses-may result in metastability, skipped transitions, or undefined output behavior, particularly at temperature extremes.

Is SN74ALS109ADG4 pin-compatible with SN74LS109N?

Yes, SN74ALS109ADG4 is pin-compatible with SN74LS109N in the same package variant: both use 16-pin PDIP (N) or SOIC (D) footprints with identical pin assignments (1CLR, 1J, 1K, 1CLK, 1PRE, 1Q, 1Q̅, GND, VCC, 2Q̅, 2PRE, 2CLK, 2K, 2J, 2CLR, 2Q). The SDAS198B datasheet confirms identical pinouts across ALS and LS versions for D and N packages, enabling direct PCB-level substitution without layout changes.

SN74ALS109ADG4 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74ALS

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tube

Product Status:: Discontinued at Digi-Key

Function:: Set(Preset) and Reset

Type:: JK Type

Output Type:: Complementary

Number of Elements:: 2

Number of Bits per Element:: 1

Clock Frequency:: 34 MHz

Max Propagation Delay @ V, Max CL:: 18ns @ 5V, 50pF

Trigger Type:: Positive Edge

Current - Output High, Low:: 400µA, 8mA

Voltage - Supply:: 4.5V ~ 5.5V

Current - Quiescent (Iq):: 4 mA

Input Capacitance:: -

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

SN74ALS109ADG4 FAQ

1.How can I place an order for SN74ALS109ADG4 through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74ALS109ADG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74ALS109ADG4 reliable?

The price and inventory of SN74ALS109ADG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74ALS109ADG4 is usually 5 days.

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SN74ALS109ADG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74ALS109ADG4 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74ALS109ADG4?

For technical support, including SN74ALS109ADG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74ALS109ADG4 requirements.

6.How does Aetrix verify that SN74ALS109ADG4 is sourced from the original manufacturer or authorized distributors?

All SN74ALS109ADG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74ALS109ADG4 meets industry standards.

7.What is the process for return or replacement of SN74ALS109ADG4?

All SN74ALS109ADG4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74ALS109ADG4, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74ALS109ADG4 part is unused and in its original packaging.

Return procedure for SN74ALS109ADG4:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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