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Home > Products > Integrated Circuits (ICs) > Logic > Signal Switches, Multiplexers, Decoders

Texas Instruments SN74ALS158NSR

Name: SN74ALS158NSR
Brand: Texas Instruments
SKU: SN74ALS158NSR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74ALS158NSR

Manufacturer:: Texas Instruments

Category:: Signal Switches, Multiplexers, Decoders

Package:: 16-SOIC (0.209", 5.30mm Width)

Datasheet:: SN74ALS158NSR.pdf

Description:: IC MULTIPLEXER 4 X 2:1 16SO

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Product details

Overview

SN74ALS158NSR from Texas Instruments is a quad 2-line-to-1-line data selector/multiplexer with inverted output logic, designed for high-speed TTL-compatible digital systems. It features buffered inputs and outputs, a common strobe (G) enable, and selects one of two 4-bit data sources (A or B) to drive four inverted outputs (1Y–4Y). It operates from 0°C to 70°C with V_CC = 4.5–5.5 V and delivers t_PHL/t_PLH as low as 2 ns (typ) on A/B→Y paths under AS-family conditions.

For engineers reviewing the SN74ALS158NSR datasheet, SN74ALS158NSR pinout, SN74ALS158NSR application, or SN74ALS158NSR equivalent, this device serves as a legacy-compatible, low-propagation-delay multiplexer for bus routing, address selection, and signal gating in industrial control logic, test equipment, and retro-computing system upgrades where inverted output polarity and ALS-series noise immunity are required.

Technical Context

The SN74ALS158NSR implements true 4-channel 2:1 multiplexing using bipolar ALS (Advanced Low-power Schottky) technology. Its internal architecture includes input inverters, AND-OR logic gates, and output drivers that collectively produce inverted output data - distinguishing it from the non-inverting SN74ALS157A family. The strobe (G) input enables or disables all outputs simultaneously in active-low fashion.

All four data channels share identical timing behavior: propagation delays are specified separately for data inputs (A/B), select input (A/B), and strobe (G), with worst-case t_PHL/t_PLH ≤ 18 ns at V_CC = 4.5–5.5 V, C_L = 50 pF, and T_A = min–max. Output drive capability supports I_OL = 8 mA (min) and I_OH = −0.4 mA (min), meeting standard TTL fan-out requirements.

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	4.5 V to 5.5 V - Ensures compatibility with standard 5-V TTL power rails and tolerates supply ripple without functional degradation.
Operating Temperature	0°C to 70°C - Qualified for commercial-grade applications including industrial controllers and instrumentation.
t_PHL, A/B → Y (max)	18 ns - Enables reliable operation in 50-MHz-equivalent synchronous logic paths with margin for trace delay and skew.
I_OL (min)	8 mA - Drives up to 20 standard TTL loads directly, eliminating need for external buffer stages in most logic interfaces.
Output Polarity	Inverted - Outputs reflect logical complement of selected input; simplifies design when downstream logic expects active-low enable or decode signals.
Input Thresholds	V_IL ≤ 0.8 V, V_IH ≥ 2.0 V - Provides robust noise margin (>0.4 V) against ground bounce and crosstalk in dense PCB layouts.
ICC (max)	10 mA at V_CC = 5.5 V - Supports low-static-power system design compared to earlier 74LS series while retaining speed.

Pinout & Package

SOP (Small Outline Package) NS, 16-pin, 0.635 mm pitch, 10.4 mm × 5.3 mm body, 2.00 mm max height, RoHS-compliant NiPdAu lead finish, MSL Level-1.

Pin/Terminal	Circuit Role	Design Meaning
1	1A	Data input channel 1, source A - Connects to first bit of primary data bus A; referenced in function table for Y1 generation.
2	1B	Data input channel 1, source B - Alternate input for same output; allows dual-source selection per channel.
3	2A	Data input channel 2, source A - Second bit of A-bus; paired with 2B for independent 2:1 mux per bit position.
4	2B	Data input channel 2, source B - Enables independent selection between two parallel 4-bit words.
5	3A	Data input channel 3, source A - Third bit of A-bus; maintains consistent 4-channel structure across all pins.
6	3B	Data input channel 3, source B - Supports full-word multiplexing without external gating logic.
7	4A	Data input channel 4, source A - Final bit of A-bus; completes 4-bit word selection capability.
8	4B	Data input channel 4, source B - Completes dual-source support for all four data lines.
9	G	Strobe (enable) input - Active-low global enable; forces all outputs high-impedance when asserted (G = H).
10	A/B	Select control - Determines whether A or B inputs are routed to outputs; low = A selected, high = B selected.
11	4Y	Inverted output channel 4 - Complement of selected 4A/4B input; driven only when G = L and A/B state matches selection.
12	3Y	Inverted output channel 3 - Matches 3A/3B per A/B state; synchronized with other Y outputs under same strobe timing.
13	2Y	Inverted output channel 2 - Provides bit-level inversion without additional gate stages.
14	1Y	Inverted output channel 1 - Primary output for LSB routing; exhibits same propagation delay profile as other Y pins.
15	V_CC	Positive supply - Must be decoupled locally (0.1 µF ceramic + 10 µF tantalum) to maintain switching integrity.
16	GND	Ground reference - Shared return path for all inputs, outputs, and internal logic; requires low-inductance PCB connection.

Key Features

Feature	Design Value
Inverted output logic	Eliminates need for external inverters in active-low bus enable or decode applications, reducing component count and board area.
ALS process technology	Delivers 2× speed improvement over standard LS TTL with comparable power consumption, enabling higher clock rates in legacy designs.
Buffered inputs and outputs	Provides high noise immunity (≥0.4 V) and consistent drive strength across temperature, critical for multi-load fan-out in noisy environments.
Common strobe (G) control	Allows synchronized enable/disable of all four outputs with single signal, simplifying timing-critical bus arbitration and power gating.
SOP-16 (NS) packaging	Enables surface-mount assembly with industry-standard footprint, compatible with automated pick-and-place and reflow processes.

Applications

Industrial PLC I/O Expansion	Legacy Computer Address Bus Switching
Use Scenario: Routing discrete sensor inputs or actuator outputs through shared backplane data lanes in modular programmable logic controllers. IC Role / Device Role / Timing Role: Quad 2:1 multiplexer selecting between local I/O and remote expansion module data streams under microcontroller command. Use Value: Reduces interconnect complexity by consolidating four independent 2-source selections into one IC, minimizing PCB layer count and signal routing congestion.	Use Scenario: Dynamically switching CPU address lines between main memory and peripheral register banks in 8-bit microcomputer systems (e.g., Z80, 6502). IC Role / Device Role / Timing Role: Address decoder front-end that routes upper address bits to alternate memory-mapped peripherals based on bank-select signal. Use Value: Enables 64 KB address space partitioning without adding propagation delay beyond 18 ns, preserving system timing margins.
Digital Test Equipment Signal Gating	Automated Manufacturing Fixture Logic
Use Scenario: Isolating DUT (device under test) signals during calibration sequences to prevent interference from stimulus generators. IC Role / Device Role / Timing Role: Controlled signal gate that blocks or passes test vectors to DUT inputs using strobe-synchronized enable. Use Value: Guarantees clean signal transitions with <2 ns jitter on enable edges, critical for sub-20 ns timing verification accuracy.	Use Scenario: Managing multiple sensor inputs (limit switches, photoeyes) and actuator outputs (solenoids, relays) in electro-mechanical assembly stations. IC Role / Device Role / Timing Role: Input multiplexer feeding PLC scan cycle, selecting among redundant sensors or diagnostic test points. Use Value: Provides deterministic 18 ns max delay across all four channels, ensuring synchronized status reporting within single PLC scan period.

Industrial PLC I/O Expansion

Legacy Computer Address Bus Switching

Use Scenario: Routing discrete sensor inputs or actuator outputs through shared backplane data lanes in modular programmable logic controllers.

IC Role / Device Role / Timing Role: Quad 2:1 multiplexer selecting between local I/O and remote expansion module data streams under microcontroller command.

Use Value: Reduces interconnect complexity by consolidating four independent 2-source selections into one IC, minimizing PCB layer count and signal routing congestion.

Use Scenario: Dynamically switching CPU address lines between main memory and peripheral register banks in 8-bit microcomputer systems (e.g., Z80, 6502).

IC Role / Device Role / Timing Role: Address decoder front-end that routes upper address bits to alternate memory-mapped peripherals based on bank-select signal.

Use Value: Enables 64 KB address space partitioning without adding propagation delay beyond 18 ns, preserving system timing margins.

Digital Test Equipment Signal Gating

Automated Manufacturing Fixture Logic

Use Scenario: Isolating DUT (device under test) signals during calibration sequences to prevent interference from stimulus generators.

IC Role / Device Role / Timing Role: Controlled signal gate that blocks or passes test vectors to DUT inputs using strobe-synchronized enable.

Use Value: Guarantees clean signal transitions with <2 ns jitter on enable edges, critical for sub-20 ns timing verification accuracy.

Use Scenario: Managing multiple sensor inputs (limit switches, photoeyes) and actuator outputs (solenoids, relays) in electro-mechanical assembly stations.

IC Role / Device Role / Timing Role: Input multiplexer feeding PLC scan cycle, selecting among redundant sensors or diagnostic test points.

Use Value: Provides deterministic 18 ns max delay across all four channels, ensuring synchronized status reporting within single PLC scan period.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad 2:1 multiplexer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74ALS157ANSR	Non-inverting output logic; otherwise identical pinout, timing, and electrical specs.	Requires downstream inversion if active-high enable or true-data routing is needed.	Select SN74ALS157ANSR when system logic expects non-inverted multiplexed data; verify compatibility with existing truth tables.
SN74AS158N	Faster propagation (1–5 ns typical), higher I_OL (20 mA), but higher ICC (15.6–22.5 mA) and PDIP-only packaging.	Better suited for high-speed, low-latency paths but incompatible with SOP-based layouts and consumes more power.	Choose SN74AS158N only when sub-10 ns delay is mandatory and board space allows through-hole mounting and thermal management.

Compared with SN74ALS157ANSR and SN74AS158N, the SN74ALS158NSR offers optimal balance of inverted-output functionality, SOP-16 surface-mount compatibility, and ALS-series power-speed trade-off - making it the preferred choice for space-constrained, noise-immune commercial systems requiring deterministic inverted multiplexing.

Availability

SN74ALS158NSR is available at Aetrix Electronics and suitable for industrial control systems, legacy computer upgrades, and automated test equipment requiring stable component supply and long-term obsolescence mitigation.

Supply support for SN74ALS158NSR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic solutions with deep heritage in TTL and advanced logic families.

The SN74ALS158NSR belongs to TI's legacy Advanced Low-power Schottky (ALS) logic product line, engineered for high-speed, low-noise digital interfacing in commercial-grade industrial and computing applications.

FAQ

What is the output logic polarity of the SN74ALS158NSR?

The SN74ALS158NSR provides inverted output logic: when input A is selected, output Y equals NOT(A); when B is selected, Y equals NOT(B). This is explicitly defined in the function table and distinguishes it from the non-inverting SN74ALS157A. The SN74ALS158NSR achieves this via internal inverter stages before the output gates, minimizing added propagation delay while delivering complementary data.

Does the SN74ALS158NSR support 3-state outputs?

No, the SN74ALS158NSR does not feature 3-state outputs. Its outputs are push-pull (totem-pole) and always driven - either high or low - when enabled. The strobe (G) input disables all outputs by forcing them high (logic 1), not high-impedance. For true 3-state operation, consider alternatives like SN74ALS257 or SN74ALS258, which include output-enable controls.

Can the SN74ALS158NSR operate at 3.3 V?

No, the SN74ALS158NSR is not rated for 3.3 V operation. Its absolute maximum V_CC is 7 V, but recommended operating range is strictly 4.5 V to 5.5 V. At 3.3 V, input thresholds (V_IH ≥ 2.0 V, V_IL ≤ 0.8 V) would be violated, and output drive strength collapses - VOH falls below 2.4 V and VOL rises above 0.5 V, risking logic misinterpretation. Use 74LVC or 74AUP series for 3.3-V-compatible multiplexers.

What is the maximum clock rate supported by the SN74ALS158NSR in a synchronous design?

While not a clocked device, the SN74ALS158NSR supports data switching up to ~50 MHz in practice. With worst-case propagation delay of 18 ns and setup/hold times implicitly satisfied by its combinatorial nature, it can reliably route signals in systems with >20 ns minimum pulse widths. For synchronous bus applications, ensure address/data valid windows exceed 18 ns plus PCB trace delay - verified in the SN74ALS158NSR switching characteristics table under V_CC = 4.5–5.5 V, C_L = 50 pF conditions.

Is the SN74ALS158NSR pin-compatible with the SN74LS158?

Yes, the SN74ALS158NSR is pin-compatible with the SN74LS158 in the same SOP-16 (NS) package. Both share identical pin assignments, electrical interface definitions, and functional behavior - though the SN74ALS158NSR offers faster propagation (18 ns max vs. 25 ns max), lower ICC (10 mA vs. 19 mA), and improved noise immunity. No PCB changes are required for drop-in replacement in existing LS-based designs seeking performance uplift.

SN74ALS158NSR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74ALS

Package/Case:: 16-SOIC (0.209", 5.30mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Type:: Multiplexer

Circuit:: 4 x 2:1

Independent Circuits:: 1

Current - Output High, Low:: 400µA, 8mA

Voltage Supply Source:: Single Supply

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: 0°C ~ 70°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SO

SN74ALS158NSR FAQ

1.How can I place an order for SN74ALS158NSR through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74ALS158NSR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74ALS158NSR reliable?

The price and inventory of SN74ALS158NSR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74ALS158NSR is usually 5 days.

3.What payment methods are accepted for SN74ALS158NSR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74ALS158NSR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74ALS158NSR?

SN74ALS158NSR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74ALS158NSR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74ALS158NSR?

For technical support, including SN74ALS158NSR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74ALS158NSR requirements.

6.How does Aetrix verify that SN74ALS158NSR is sourced from the original manufacturer or authorized distributors?

All SN74ALS158NSR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74ALS158NSR meets industry standards.

7.What is the process for return or replacement of SN74ALS158NSR?

All SN74ALS158NSR units undergo pre-shipment inspection (PSI). If there is an issue with SN74ALS158NSR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74ALS158NSR part is unused and in its original packaging.

Return procedure for SN74ALS158NSR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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